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| Number | Title | Issue Date |
| 5280595 | State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status f... | 01/18/1994 |
| 5276888 | Computer system with interrupts transparent to its operating system and application programs A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the... | 01/04/1994 |
| 5265236 | Method and apparatus for increasing the speed of memory access in a virtual memory system having fast page mode In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing ... | 11/23/1993 |
| 5249278 | Microprocessor breakpoint apparatus A breakpoint apparatus incorporated in a single chip microprocessor. The apparatus permits breakpoints on specific references to either program instructions or data. The width of the breakpoint address can be varied, the apparatus includes a logic circuit... | 09/28/1993 |
| 5237668 | Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory progr... | 08/17/1993 |
| 5230045 | Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain... | 07/20/1993 |
| 5226138 | Method for selectively transferring data instructions to a cache memory A cache controller is coupled between a central processing unit (CPU) and a memory management unit (MMU). The MMU is coupled to main memory, and the cache controller is further coupled to a cache memory. A cache controller transfers a block of N programmi... | 07/06/1993 |
| 5214775 | Hierarchy structured memory system contained in a multiprocessor system A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disp... | 05/25/1993 |
| 5212776 | Computer system comprising a main bus and an additional communication means directly connected between processor and main memory A processor in a computer system is connected, together with one or more control units of peripheral apparatus, to the main memory via a main bus. For a very fast processor the storage capacity of the main memory should be so high that the full physical a... | 05/18/1993 |
| 5212778 | Message-driven processor in a concurrent computer A message-driven concurrent computer system stores incoming messages in a row buffer and then in a queue in main memory. A translator cache is also located in main memory, and output from the cache is through a set of comparators. Both the queue and cache... | 05/18/1993 |
| 5193202 | Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than ... | 03/09/1993 |
| 5144692 | System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. On... | 09/01/1992 |
| 5111389 | Aperiodic mapping system using power-of-two stride access to interleaved devices An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory syste... | 05/05/1992 |
| 5016169 | Data processor capable of correctly re-executing instructions A data processor includes a bus interface coupled to an external bus for transferring information to and from the external bus, an instruction decoding section coupled to the bus interface to receive an instruction through the bus interface from the exter... | 05/14/1991 |
| 5016166 | Method and apparatus for the synchronization of devices The system of the present invention provides for the synchronization of access devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. ... | 05/14/1991 |
| 4991081 | Cache memory addressable by both physical and virtual addresses A cache memory addressable by both physical and virtual addresses includes a cach data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories a... | 02/05/1991 |
| 4989137 | Computer memory system A computer memory system for use with a user processor provides automatic memory operations independently of the user processor. The memory system includes a logical memory system which is accessed by the user processor through a binding register unit, en... | 01/29/1991 |
| 4970642 | An apparatus for accessing a memory In an apparatus for controlling the access of a memory, a memory is accessed in accordance with a physical address composed of a predetermined number of bits larger than another predetermined number of which a logical address is composed. For the purpose,... | 11/13/1990 |
| 4959770 | Data processing system employing two address translators, allowing rapid access to main storage by input/output units In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection u... | 09/25/1990 |
| 4916608 | Provision of virtual storage resources to an operating system control program Method and apparatus for dynamically providing virtual storage resources to an operating system control program in a computing complex where the control program controls the concurrent execution of multiple virtual machines confer on the control program t... | 04/10/1990 |
| 4873521 | Address administration unit of a multi-processor central control unit of a communications switching system An address management unit is provided for the conversion of logical addresses contained in a program into physical addresses for a multi-processor central control unit of a computer-controlled communications switching system comprising a central bulk sto... | 10/10/1989 |
| 4761733 | Direct-execution microprogrammable microprocessor system A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction addres... | 08/02/1988 |
| 4677546 | Guarded regions for controlling memory access In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. ... | 06/30/1987 |
| 4669043 | Memory access controller The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access cont... | 05/26/1987 |
| 4623962 | Register control processing system This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the req... | 11/18/1986 |
| 4520441 | Data processing system A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current ins... | 05/28/1985 |
| 4471432 | Method and apparatus for initiating the execution of instructions using a central pipeline execution unit A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction f... | 09/11/1984 |
| 4297743 | Call and stack mechanism for procedures executing in different rings A procedure call mechanism implemented by hardware instructions and a hardware recognizable mechanism known as a stack. A procedure call is utilized by users who have written their programs in a modular way to pass from one program module to another, it i... | 10/27/1981 |
| 4257101 | Hardware in a computer system for maintenance by a remote computer system A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer syst... | 03/17/1981 |
| 4084228 | Process management structures and hardware/firmware control A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows: 1. Running... | 04/11/1978 |
| 4004278 | System for switching multiple virtual spaces In a virtual memory system capable of embodying therein multiple virtual spaces used in a switching mode and having a high speed memory for storing address sets each including a virtual address of the virtual space and a real address of a real space corre... | 01/18/1977 |
