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| Number | Title | Issue Date |
| 5301340 | IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file loca... | 04/05/1994 |
| 5291599 | Dispatcher switch for a partitioner A computer partitioner provides services to several partitions coexisting in a computer at one time. To operate efficiently, certain applications executing within a partition will intermittently require specific services to be delivered to them in a timel... | 03/01/1994 |
| 5289470 | Flexible scheme for buffer space allocation in networking devices A method and apparatus for storing a data packet in a networking device. The networking device has a plurality of buffers. Each buffer has a respective size. A predetermined, ordered sequence of buffer sets is established. A buffer is allocated from the p... | 02/22/1994 |
| 5276884 | Controlling the initiation of logical systems in a data processing system with logical processor facility In a computer system that has one or more primary processing units processing user tasks and at least one auxiliary processing unit servicing the primary processing units, feature control is performed by storing a authorization code in the auxiliary proce... | 01/04/1994 |
| 5268768 | Transmitting method and transmitting apparatus of stored information of memory In an apparatus for transmitting stored information from memory, the store area of memory is divided according to a predetermined store capacity. The data is transmitted from the divided store area. A transmission for the store areas is also stored. When ... | 12/07/1993 |
| 5247687 | Method and apparatus for determining and using program paging characteristics to optimize system productive CPU time Paging data is used to manage address space working set size, system multiprogramming level, and job mix, to improve system productive CPU utilization. System paging characteristics are monitored to determine when to perform management functions. When nee... | 09/21/1993 |
| 5237460 | Storage of compressed data on random access storage devices A random-access type storage device such as a hard disk or semiconductor memory is formatted to provide multiple partitions of varying block size. The data to be stored is in blocks of fixed size, and these blocks are compressed if the compressed size fit... | 08/17/1993 |
| 5210854 | System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version Firmware resident in electrically erasable programmable read only memory ("EEPROM") can be updated by a user while maintaining the intelligence of a computer system during the updating process by a control logic device. The control logic device decodes ad... | 05/11/1993 |
| 5193202 | Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than ... | 03/09/1993 |
| 5136706 | Adaptive memory management system for collection of garbage in a digital computer A memory management system for a digital computer divides a virtual memory space into regions. Each region has attributes indicating generation, volatility, and activity. During garbage collection, memory objects referenced by normal program execution are... | 08/04/1992 |
| 5129074 | Data string storage device and method of storing and retrieving data strings A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an interna... | 07/07/1992 |
| 5097414 | Buffer-storage control system for simultaneously accessible partitions of tag and data blocks of buffer storage A buffer-storage control system used in a pipeline data processor includes a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage having tag portion and a data portion, each portion being composed of a pl... | 03/17/1992 |
| 5047989 | Chapter mode selection apparatus for MOS memory An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memor... | 09/10/1991 |
| 5034887 | Microprocessor with Harvard Architecture A microprocessor utilizing Harvard Architecture is disclosed with a data space for data storage, an instruction space for instruction storage, and a common space implemented as a high-speed on-chip RAM that functions as a continuous extension of both the ... | 07/23/1991 |
| 5033021 | Method of recording successive balances in an electronic memory, and a system for implementing said method A method of recording successive balances in an electronic memory constituted by a plurality of memory locations each having an initial state "0" and a final or "written" state "1". The memory includes at least one memory region split into two memory zone... | 07/16/1991 |
| 5012408 | Memory array addressing system for computer systems with multiple memory arrays A computer system has a set of memory module slots, each of which may receive a memory module or may be left empty. The memory slots are arranged to accept at least two different types of memory modules having different amounts of memory storage. Each typ... | 04/30/1991 |
| 4964035 | Vector processor capable of high-speed access to processing results from scalar processor A vector processing system having a main storage, a vector processor, a scalar processor, and an address translation mechanism in each processor in which data is stored in the main processor. The vector processing system includes a common memory in which ... | 10/16/1990 |
| 4951246 | Nibble-mode dram solid state storage device A nibble-mode DRAM solid state storage device is organized into a plurality of sections each including a plurality of groups, each including a plurality of ranks of DRAM memory chips. A pipeline data path is provided into and out of each group and nibble-... | 08/21/1990 |
| 4947477 | Partitionable embedded program and data memory for a central processing unit A central processing unit with partitionable program and data memory includes a CRT (10) which is interfaced with an embedded program/data memory (14). The embedded memory (14) is a random access memory which has a user-defined partition address that defi... | 08/07/1990 |
| 4903234 | Memory system In a memory system having a storage device and a key storage keeping key data controlling an access to the storage device, there is disposed a key address translation structure for obtaining an address of an entry of the key storage based on an address of... | 02/20/1990 |
| 4901276 | Portable electronic apparatus having a function of checking for empty areas in which to write data The portable electronic apparatus of the invention has a memory for storing externally-supplied data, and a central processing unit (CPU 15) for accessing the memory. The memory is divided into a plurality of areas. Each area has pointer data indicating a... | 02/13/1990 |
| 4887234 | Portable electronic device with plural memory areas A portable electronic device in which storage data supplied from an external device is stored in a deletable EEPROM or in a non-deletable EPROM in accordance with specified data added to the storage data and an indication of whether or not the storage dat... | 12/12/1989 |
| 4841432 | Method of reconfiguration of storage areas in an apparatus for cheating NC tapes In an apparatus wherein a memory is subdivided into plural storage areas, and predetermined data are adapted to be written into respective ones of the storage areas, a method of reconfiguring the storage areas of the memory. The leading addresses of the r... | 06/20/1989 |
| 4807179 | Method and device for recording analog parameters on a static digital memory A method and apparatus are provided for data storage in, for example, a black box for an aircraft. A static digital memory is divided into three portions, A, B and C. Data is read into successive sequential portions of wrap-around memory portion A. When a... | 02/21/1989 |
| 4758944 | Method for managing virtual memory to separate active and stable memory blocks A pointer, N, indicates an address in a virtual memory space of a demand paged memory including a plurality of virtual address pages and a fixed number of physical memory pages into which blocks of information can be written. A back-up memory store is pro... | 07/19/1988 |
| 4695949 | Method for efficient support for reference counting A method and apparatus for managing a block oriented memory of the type in which each memory block has an associated reference count representing the number of pointers to it from other memory blocks and itself. Efficient and cost-effective implementation... | 09/22/1987 |
| 4674032 | High-performance pipelined stack with over-write protection A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up t... | 06/16/1987 |
| 4638425 | Peripheral data storage having access controls with error recovery Data supplied to a data storage system by a host processor has one of two use status. A first use status is that the supplied data is to be retentively stored in the data storage system. A second use status is that the supplied data is exempted from the r... | 01/20/1987 |
| 4607346 | Apparatus and method for placing data on a partitioned direct access storage device A storage device, such as a direct access storage device, is partitioned into a plurality of partitioned devices having different access and storage characteristics matched to the required perforamnce. Data may be stored on that partitioned device which m... | 08/19/1986 |
| 4600986 | Pipelined split stack with high performance interleaved decode A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input reques... | 07/15/1986 |
| 4580211 | Method for controlling storage of data sets in memory unit In a computer system, there is provided the information representing empty areas generated when data sets are stored in a magnetic disk apparatus. From that information, the total capacity of empty areas and the deree of nonuniformity in size of empty are... | 04/01/1986 |
| 4519032 | Memory management arrangement for microprocessor systems A memory management system is structured for use with a self-contained microprocessor to form a multi-user computer. The system operates to establish user and kernel modes each having different operating permissions. When the system is operating in the us... | 05/21/1985 |
| 4468729 | Automatic memory module address assignment system for available memory modules An automatic Memory Module sensing and Memory Module address assignment system during an initializing sequence is described. Each Memory Module has a memory assignment register associated therewith, and all memory assignment registers are initialized to a... | 08/28/1984 |
| 4467421 | Virtual storage system and method A virtual storage system for use in conjunction with a host computer is disclosed. The system features a memory control processor external to the host computer which divides user-defined data sets into blocks of a size convenient for storage on, e.g., mag... | 08/21/1984 |
| 4455619 | Interactive equipment for computer programming by linkage of labeled block representations of arithmetic/logical subprograms A programming equipment is used for automatically constructing programs by selecting and interconnecting a plurality of previously prepared unit programs in accordance with instructions by an operator. A screen of a display unit is divided into a pluralit... | 06/19/1984 |
| 4430712 | Adaptive domain partitioning of cache memory space A method of operation of a memory array for storage of records of differing predetermined sizes is disclosed which features division of the array into domains which are substantially integral multiples of the predetermined record sizes. In a preferred emb... | 02/07/1984 |
| 4378594 | High speed to low speed data buffering means A system is provided in which a memory is divided into two parts, so that a substantially continuous printing operation can be carried out by reading information to be printed from one part of the memory, with printing being interrupted for brief periods ... | 03/29/1983 |
| 4333160 | Memory control system A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for suppl... | 06/01/1982 |
| 4189781 | Segmented storage logging and controlling A system and method are disclosed for controlling text storage in a text processing system using a segmented, serial bulk storage device. A plurality of storage segments of equal length are further subdivided into portions of equal length. A typical page ... | 02/19/1980 |
| 4044334 | Database instruction unload One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which determines the appropriate register w... | 08/23/1977 |
