Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 6954206 | Data processor having unified memory architecture using register to optimize memory access In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 | 10/11/2005 |
| 6954836 | System and method for processor with predictive memory retrieval assist A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the ... | 10/11/2005 |
| 6950918 | File management of one-time-programmable nonvolatile memory devices An embodiment of the present invention includes a digital equipment system comprising a host for sending commands to read or write files having sectors of information, each sector having and being modifyable on a bit-by-bit, byte-by-byte or word-by-word basis. The h... | 09/27/2005 |
| 6950909 | System and method for reducing contention in a multi-sectored cache A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache directory updates. When a first queue issues a write access request for a f... | 09/27/2005 |
| 6948011 | Alternate Register Mapping A novel method of providing alternate access to a storage element for holding a data element in a network interface. The storage element is accessed via a first access path when the network interface operates with a first type of software, and via a second access pa... | 09/20/2005 |
| 6948005 | Peripheral device for programmable controller A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices o... | 09/20/2005 |
| 6944063 | Non-volatile semiconductor memory with large erase blocks storing cycle counts In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such a... | 09/13/2005 |
| 6944739 | Register bank A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and co... | 09/13/2005 |
| 6944737 | Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buf... | 09/13/2005 |
| 6941415 | DRAM with hidden refresh A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh ... | 09/06/2005 |
| 6941421 | Zero delay data cache effective address generation A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode in the cache access path, and to replace the address generation adder m... | 09/06/2005 |
| 6938142 | Multi-bank memory accesses using posted writes Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read... | 08/30/2005 |
| 6938129 | Distributed memory module cache One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 08/30/2005 |
| 6938133 | Memory latency and bandwidth optimizations A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory mod... | 08/30/2005 |
| 6934824 | Dual-port memory controller for adjusting data access timing A dual-port memory controller having a memory controller and at least one delaying unit. Since the memory controller executes a data access by selecting one processor, the memory controller outputs at least one request disapproval signal indicating that it cannot ac... | 08/23/2005 |
| 6934822 | Organization of multiple snapshot copies in a data storage system A file server maintains a production file system supported by a clone volume, and multiple snapshot file systems supported by respective save volumes in a snapshot queue. Before a data block is modified for the first time after creation of the youngest snapshot, the... | 08/23/2005 |
| 6931506 | Electronic device for data processing, such as an audio processor for an audio/video decoder An electronic device for data processing may include p synchronous processor cores each respectively clocked by one of p clock signals all having a same period T and being phase-shifted by 2π/p relative to one other. The electronic device may further include a sing... | 08/16/2005 |
| 6931498 | Status register architecture for flexible read-while-write device A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status re... | 08/16/2005 |
| 6931499 | Method and apparatus for copying data between storage volumes of storage systems The present invention provides systems and methods for copying and/or transferring stored data of one storage volume of a storage system to another storage volume while enabling requests to the storage volumes. The systems and methods may be particularly useful in R... | 08/16/2005 |
| 6928027 | Virtual dual-port synchronous RAM architecture Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional architecture used with a single-port RAM. Disclosed is a read/write memory de... | 08/09/2005 |
| 6928525 | Per cache line semaphore for cache access arbitration A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whet... | 08/09/2005 |
| 6925569 | Secured microprocessor comprising a system for allocating rights to libraries A secured microprocessor includes a rights allocation system for the allocation, to programs executable by the microprocessor, of permanent access rights to certain zones of the memory array of the microprocessor. The rights allocation system confers, on a sub-progr... | 08/02/2005 |
| 6925534 | Distributed memory module cache prefetch One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 08/02/2005 |
| 6925536 | Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 08/02/2005 |
| 6922758 | Synchronous flash memory with concurrent write and read operation A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an exte... | 07/26/2005 |
| 6922760 | Distributed result system for high-performance wide-issue superscalar processor A system for handling distributed results in a high-performance wide-issue superscalar processor having result-forwarding capability is disclosed. The system generally includes buffer logic configured to produce write data and write information to a register file. T... | 07/26/2005 |
| 6920634 | Detecting and causing unsafe latent accesses to a resource in multi-threaded programs Methods and systems for analyzing multi-threaded programs are provided. The predisposed execution of multi-threaded programs is modified to cause and detect latent unsafe accesses to a resource, such as a memory location. It is first determined that unsynchronized a... | 07/19/2005 |
| 6920512 | Computer architecture and system for efficient management of bi-directional bus An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus ... | 07/19/2005 |
| 6919592 | Electromechanical memory array using nanotube ribbons and method for making same Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports... | 07/19/2005 |
| 6918019 | Network and networking system for small discontiguous accesses to high-density memory devices A networking system consists of multiple computing devices connected to multiple networking processing engines each containing a memory system including a random access device (RAM). The RAM device contains a memory controller which performs memory read and write re... | 07/12/2005 |
| 6915400 | Memory access collision avoidance scheme A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are g... | 07/05/2005 |
| 6912637 | Apparatus and method for managing memory in a network switch The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providin... | 06/28/2005 |
| 6911682 | Electromechanical three-trace junction devices Three trace electromechanical circuits and methods of using same are described. A circuit includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. The nanotube ribbon is movable to... | 06/28/2005 |
| 6912598 | Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selectiv... | 06/28/2005 |
| 6910095 | Memory request handling method for small discontiguous accesses to high-density memory devices A memory read and write request handling method is performed by a memory controller which buffers incoming memory read and write requests and distributes the requests across multiple memory banks of a memory system in connection with client processes. The read and w... | 06/21/2005 |
| 6910114 | Adaptive idle timer for a memory device Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number ... | 06/21/2005 |
| 6904469 | Storage control apparatus In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be proces... | 06/07/2005 |
| 6904505 | Method for determining valid bytes for multiple-byte burst memories A memory controller for a multi-byte burst memory device may control access to memory based on parameters set up by a client. These parameters may include a byte address and a byte count that indicates the number of bytes the client is requesting from memory. These ... | 06/07/2005 |
| 6898690 | Multi-tiered memory bank having different data buffer sizes with a programmable bank select An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor. ... | 05/24/2005 |
| 6895473 | Data control device and an ATM control device A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of... | 05/17/2005 |
