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| Number | Title | Issue Date |
| 5495601 | Method to off-load host-based DBMS predicate evaluation to a disk controller A method is disclosed for a database system for [off-loading] off-loading, to disk [controller] controller, the extraction of committed [data involving the] data. The system first [picking] picks a Commit-- LSN value and [insuring] insures all ... | 02/27/1996 |
| 5493669 | Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffe... | 02/20/1996 |
| 5490263 | Multiported buffer memory system for disk drive complex A multiported buffer memory system provides access to four external sources which can access data words in any one of four memory modules. The functions of Reading and Writing and status information can occur simultaneously during the course of system cyc... | 02/06/1996 |
| 5490265 | Late cancel method and apparatus for a high performance microprocessor system A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporate... | 02/06/1996 |
| 5454095 | Multi-processor system in which at least two processors access the same memory A multi-processor system that is useful for controlling processes of motor vehicles. The system having at least two processors that jointly access the same memory. The system memory is divided into at least two sectors. A first processor accesses one memo... | 09/26/1995 |
| 5444722 | Memory module with address error detection A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a ma... | 08/22/1995 |
| 5432908 | High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is e... | 07/11/1995 |
| 5381536 | Method and apparatus for separate mark and wait instructions for processors having multiple memory ports The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of ... | 01/10/1995 |
| 5301340 | IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file loca... | 04/05/1994 |
| 5274792 | Information processing apparatus with parallel instruction decoding An information processing apparatus includes a decoder for decoding an instruction, a general purpose register part including a stack pointer and a plurality of general purpose registers, a special purpose register part including a plurality of special pu... | 12/28/1993 |
| 5257359 | Instruction cache buffer with program-flow control A memory buffer for buffering data from an external memory to a processor including a cache memory, a first-in-first-out memory, a direct data path, a writing selector for writing data from the external memory to one of the cache memory, first-in-first-ou... | 10/26/1993 |
| 5241663 | Hierarchically pairing memory blocks based upon relative storage capacities and simultaneously accessing each memory block within the paired memory blocks An automatic memory sizer for a digital video recorder is provided. The sizer in accordance with the present invention automatically examines and configures available memory space for efficient storage of digital video information regardless of whether th... | 08/31/1993 |
| 5168558 | Apparatus and method for providing distributed control in a main memory unit of a data processing system A main memory unit for a data processing system has at least one memory board and allows each memory board to process data simultaneously. Each memory board may also include a plurality of memory array units which also can process data simultaneously. The... | 12/01/1992 |
| 5165039 | Register file for bit slice processor with simultaneous accessing of plural memory array cells A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in r... | 11/17/1992 |
| 5129074 | Data string storage device and method of storing and retrieving data strings A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an interna... | 07/07/1992 |
| 5127097 | Memory writing apparatus A memory writing apparatus for simultaneously writing the same data in a plurality of memories such as PROMs, the apparatus having a master function portion and slave function portions connected to the master function portion. A plurality of memories in w... | 06/30/1992 |
| 5113513 | Apparatus and method for loading a program in an external storage device connected to one bus into a memory connected to a different bus An address for writing data in a host memory connected to a first bus is converted into an address for writing the data in an interface memory connected to a second bus. Connection/disconnection of the data line of the first bus to/from the data line of t... | 05/12/1992 |
| 5111385 | Parallel-mode data transfer apparatus using sector memories A data transfer apparatus comprises first and second memories each having a plurality of sectors each having the storage capacity of each sector in a storage disk. First and second memory access circuits are respectively associated with the first and seco... | 05/05/1992 |
| 5010476 | Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units This invention speeds up the execution of instructions in an information processing system by tightly coupling two or more processors to a random access storage mechanism in such a manner that no arbitration is required and no processor is forced to wait ... | 04/23/1991 |
| 5008816 | Data processing system with multi-access memory A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included... | 04/16/1991 |
| 4928234 | Data processor system and method A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared s... | 05/22/1990 |
| 4910667 | Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for stori... | 03/20/1990 |
| 4817035 | Method of recording in a disk memory and disk memory system A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a... | 03/28/1989 |
| 4590586 | Forced clear of a memory time-out to a maintenance exerciser A maintenance exerciser makes requests of certain inoperative and malfunctioning storage memory bank portions of a large scale storage memory unit concurrently that normal system requestors do request of remaining, correctly functional, storage memory ban... | 05/20/1986 |
| 4571676 | Memory module selection and reconfiguration apparatus in a data processing system A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modul... | 02/18/1986 |
| 4472772 | High speed microinstruction execution apparatus N-way microprogram branching is employed in conjunction with a specially organized multiple-chip microinstruction memory in a manner which makes it possible to divide the accessing of the memory into two separate operations which can be performed simultan... | 09/18/1984 |
| 4368461 | Digital data processing device A digital data processing device in which a color memory has a temporal data storage register at input/output interface thereof so that the data write-in or data read-out operations executed by a micro-processing unit (MPU) is always performed through the... | 01/11/1983 |
| 4316244 | Memory apparatus for digital computer system Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructi... | 02/16/1982 |
| 4298931 | Character pattern display system A data processing system such as a character display system is provided with a first memory circuit for storing coded characters to be displayed, a second memory circuit for storing picture element information of characters to be displayed, and a characte... | 11/03/1981 |
| 4099256 | Method and apparatus for establishing, reading, and rapidly clearing a translation table memory A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by cor... | 07/04/1978 |
| 4099253 | Random access memory with bit or byte addressing capability Disclosed is a random access memory particularly adapted for use in a programmable controller or other similar application wherein some data is preferably handled in the form of multi-bit words or bytes and other data is preferably handled in the form of ... | 07/04/1978 |
| 4099231 | Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality... | 07/04/1978 |
| 4051551 | Multidimensional parallel access computer memory system A multidimensional parallel access computer memory system is provided to facilitate high speed parallel access of data from a multi-bank computer memory. The system is particularly adapted to matrix calculations whereby matrix elements along linear matrix... | 09/27/1977 |
| 4028663 | Digital computer arrangement for high speed memory access A data processing arrangement is disclosed including a central processing unit, a plurality of peripheral units coupled to a peripheral bus, a memory access controller, a first memory bus, and a second memory bus. The first memory bus serves a first plura... | 06/07/1977 |
