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| Number | Title | Issue Date |
| 7426607 | Memory system and method of operating memory system A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the m... | 09/16/2008 |
| 7426620 | Apparatus and method for memory access of sharing buses An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's default... | 09/16/2008 |
| 7426621 | Memory access request arbitration A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the ... | 09/16/2008 |
| 7424578 | Computer system, compiler apparatus, and operating system A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates thr... | 09/09/2008 |
| 7423981 | Method and apparatus for an incremental update of a longest prefix match lookup table A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is pro... | 09/09/2008 |
| 7424576 | Parallel cachelets Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content store... | 09/09/2008 |
| 7421545 | Method and apparatus for multiple sequence access to single entry queue Bus address, function and system information in relation to bus requests are maintained in a centralized location (702). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations... | 09/02/2008 |
| 7421557 | Method and device for performing cache reading Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. ... | 09/02/2008 |
| 7421446 | Allocation of storage for a database Various approaches for allocating storage for a file are disclosed. In one approach, in response to each call to allocate an available portion of storage, one of a plurality of allocation approaches is selected based on a value of a file attribute associated with th... | 09/02/2008 |
| 7418566 | Memory arrangement and method for reading from a memory arrangement A memory arrangement is provided, which has a programmable memory and a first buffer memory associated with the programmable memory, to which buffer memory, in the case of a command access, at least one command following the accessed command is written. A second buf... | 08/26/2008 |
| 7415590 | Integrated circuit having a memory cell array capable of simultaneously performing a data read operation and a data write operation An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are... | 08/19/2008 |
| 7412569 | System and method to track changes in memory Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a trackin... | 08/12/2008 |
| 7404059 | Parallel copying scheme for creating multiple versions of state information State information in a processor is managed using a lookup table that has multiple memory circuits, each with multiple entries. Items of state information belonging to a first state version are stored in a first group of the entries, with each entry in the first gro... | 07/22/2008 |
| 7404058 | Method and apparatus for avoiding collisions during packet enqueue and dequeue A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or stat... | 07/22/2008 |
| 7401191 | System and method for performing disk write operations by writing to a data depot prior to an in-place write Methods, computer programs, information handling systems, and state machines for performing an atomic write to a data block area are disclosed. The atomic write is an in-place write> The method includes receiving one or more data blocks to write to the data block ar... | 07/15/2008 |
| 7398368 | Atomic operation involving processors with different memory transfer operation sizes Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address conta... | 07/08/2008 |
| 7386696 | Semiconductor memory module The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and fr... | 06/10/2008 |
| 7380062 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In... | 05/27/2008 |
| 7380076 | Information processing apparatus and method of accessing memory The present invention makes it possible to inexpensively and quickly execute a process of rewriting data stored in a memory, thus reducing the power consumption of an information processing apparatus. In connection with a conventional Read-Modify-Write function, an ... | 05/27/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
| 7376950 | Signal aggregation The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operatio... | 05/20/2008 |
| 7373460 | Media drive and command execution method thereof Embodiments of the present invention provide a media drive capable of improving command processing performance by, when a plurality of commands is queued, shortening seek time and rotational latency, and also effectively making use of the shortened period of time. I... | 05/13/2008 |
| 7373465 | Data processing system configuring and transmitting access request frames with a field in channel command words to accommendate a plurality of logical device address data therein In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it possible to expand the number of logical device addresses in excess of the device address limitations of th... | 05/13/2008 |
| 7370151 | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array ... | 05/06/2008 |
| 7370252 | Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory u... | 05/06/2008 |
| 7366831 | Lock-free bounded FIFO queue mechanism A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes... | 04/29/2008 |
| 7366828 | Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a s... | 04/29/2008 |
| 7366823 | Method and system for memory access Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data a... | 04/29/2008 |
| 7363452 | Pipelined burst memory access A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation. ... | 04/22/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7356452 | System and method for simulating performance of one or more data storage systems This invention is a system and method for simulating performance of one or more data storage systems. This invention may be used in many useful ways including for configuring or modeling a data storage environment, problem isolation, and general design. ... | 04/08/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7343446 | Concurrent data recall in a hierarchical storage environment using plural queues A technique for recalling data objects stored on media. A queue is created for each medium on which data objects are located, where each request to recall a data object is placed on the queue corresponding to the medium on which the data object is located. A queue i... | 03/11/2008 |
| 7343457 | Dual active bank memory controller A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a second path controller, and a synchronizer. The arbiter is configured t... | 03/11/2008 |
| 7343395 | Facilitating resource access using prioritized multicast responses to a discovery request Systems and methods are provided to facilitate resource access using prioritized multicast responses to a discovery request. ... | 03/11/2008 |
| 7340489 | Virtual storage devices Accessing stored data includes providing a virtual storage area having a table of pointers that point to sections of at least two other storage areas, where the virtual storage area contains no sections of data, in response to a request for accessing data of the vir... | 03/04/2008 |
| 7340582 | Fault processing for direct memory access address translation An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested... | 03/04/2008 |
| 7340558 | Multisection memory bank system A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area netwo... | 03/04/2008 |
| 7340562 | Cache for instruction set architecture A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number... | 03/04/2008 |
