Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 6775752 | System and method for efficiently updating a fully associative array The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing... | 08/10/2004 |
| 6775717 | Method and apparatus for reducing latency due to set up time between DMA transfers A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior... | 08/10/2004 |
| 6775686 | High availability redundant array of data storage elements that bridges coherency traffic In a high availability redundant array of data storage elements, one of a plurality of storage element controllers (FIG. 1, 110, 120) is interfaced to a corresponding network (150, 160). Each of the plurality of storage element controllers (110, 120... | 08/10/2004 |
| 6772311 | ATAPI device unaligned and aligned parallel I/O data transfer controller A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using r... | 08/03/2004 |
| 6772273 | Block-level read while write method and apparatus In one embodiment, a method and apparatus for reading one block of a nonvolatile memory device while writing to another block of a nonvolatile memory device is disclosed. ... | 08/03/2004 |
| 6769047 | Method and system for maximizing DRAM memory bandwidth through storing memory bank indexes in associated buffers A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the... | 07/27/2004 |
| 6769051 | Memory controller and memory control method for controlling an external memory device to be accessible even in an addressing mode that is not supported thereby A comparison circuit compares a burst access request from a bus controller with an access mode that is supported by an external memory device and that is set in a device information setting register. When the burst access request does not match the access mode that ... | 07/27/2004 |
| 6768490 | Checkerboard buffer using more than two memory devices Methods and apparatus for storing and retrieving data in parallel but in different orders, using three or more memory devices. In one implementation, data for pixels is stored according to a checkered pattern, sequentially among memory devices, forming a checkerboar... | 07/27/2004 |
| 6766429 | Low cost and high RAS mirrored memory An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant â€... | 07/20/2004 |
| 6766431 | Data processing system and method for a sector cache A data processing system (10) provides a set of user configurable control bits in a cache control register (50) that sets a cache fill policy. The data processing system also allows a cache fill policy to be dynamically set via bits in the TLB. Therefo... | 07/20/2004 |
| 6760805 | Flash management system for large page size A system and method for enabling flash memory systems to support flash devices with pages that are larger than operating system data sector sizes, while not violating the device's specifications, and also optimizing performance. According to the present invention, t... | 07/06/2004 |
| 6756987 | Method and apparatus for interleaving read and write accesses to a frame buffer Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel display. Transferring data through the single frame buffer by interleaving re... | 06/29/2004 |
| 6757792 | Storage system and method of configuring the storage system When storage controllers are added to a storage system to change the storage system from a configuration having only one storage controller to a configuration having plural storage controllers, or when storage controllers are removed from the storage system to chang... | 06/29/2004 |
| 6757799 | Memory device with pipelined address path In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture... | 06/29/2004 |
| 6757800 | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile m... | 06/29/2004 |
| 6757797 | Copying method between logical disks, disk-storage system and its storage medium A copying method, disk storage system, and storage medium for copying data from one logical disk to another logical disk, making possible immediate access, in response to a copy command. Copying from a first logical disk to a second logical disk is performed for eac... | 06/29/2004 |
| 6751717 | Method and apparatus for clock synchronization between a system clock and a burst data clock The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage eleme... | 06/15/2004 |
| 6751711 | Methods and systems for process rollback in a shared memory parallel processor computing environment Methods and systems for process rollback in a shared memory parallel processor computing environment use priority values to control process rollback. Process classes are defined and each process class is allocated a base priority value. Each process run by the syste... | 06/15/2004 |
| 6748505 | Efficient system bus architecture for memory and register transfers A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines in which upon the falling edge of the grant signal from the memory con... | 06/08/2004 |
| 6747912 | Implied precharge and posted activate command to reduce command bandwidth A combination precharge/activate command is utilized in order to make more efficient use of a command bus between a memory controller and a system memory. Upon receiving a precharge/activate command from the memory controller, the system memory makes a determination... | 06/08/2004 |
| 6745290 | High-speed processor system and cache memories with processing capabilities The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles. The processor system in accordance with the invention has a CPU, a plu... | 06/01/2004 |
| 6745308 | Method and system for bypassing memory controller components A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memor... | 06/01/2004 |
| 6745267 | Multi-functional mini-memory card suitable for SFMI and USB interfaces A multi-functional mini-memory card serves for storing data and support data input and output. The multi-functional mini-memory card comprises a memory card I/O functional module; a memory for storing data; and a main controller connecting between the memory card I/... | 06/01/2004 |
| 6738874 | Controller architecture and strategy for small discontiguous accesses to high-density memory devices A RAM device including a memory and a memory controller. The memory controller can be configured to buffer incoming requests, prioritize the requests into a final order, and submit the requests to the memory in the final order. The final order, as needed, is selecte... | 05/18/2004 |
| 6738881 | Multi-channel DMA with scheduled ports A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (46... | 05/18/2004 |
| 6738887 | Method and system for concurrent updating of a microcontroller's program memory A system and method for concurrent operations in a microcontroller's program memory is provided. In one exemplary embodiment, a microcontroller system is provided that includes a microcontroller, programmable read-only memory (PROM), random access memory (RAM) and a... | 05/18/2004 |
| 6735679 | Apparatus and method for optimizing access to memory A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated ... | 05/11/2004 |
| 6732239 | Concurrent access scheme for exclusive mode cache Methods for permitting concurrent access to an object in a data store of the type having an exclusive access cache are disclosed. The method uses first-in-last-out conditions to control which concurrent transaction, if there is more than one transaction pending for ... | 05/04/2004 |
| 6728843 | System and method for tracking and processing parallel coherent memory accesses A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses.... | 04/27/2004 |
| 6728851 | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile m... | 04/27/2004 |
| 6721840 | Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device.... | 04/13/2004 |
| 6718430 | Window-based flash memory storage system and management and access methods thereof A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a nu... | 04/06/2004 |
| 6715024 | Multi-bank memory device having a 1:1 state machine-to-memory bank ratio A memory controller includes an input command decoder circuit for generating an input command, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state ma... | 03/30/2004 |
| 6715059 | Methods and systems for a shared memory unit with extendable functions Systems and methods are described for an enhanced shared memory unit. Embodiments of methods presented may include permitting a plurality of central processing units to simultaneously read data stored in a first shared memory address. This first shared memory addres... | 03/30/2004 |
| 6708237 | Method and apparatus for managing data access and storage of data located on multiple storage devices An apparatus and method for accessing a data item from a storage system having a plurality of data storage devices are disclosed. I/O operation requests are submitted to multiple data storage devices for each data item to be accessed. The I/O operation requests are ... | 03/16/2004 |
| 6697909 | Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is perfor... | 02/24/2004 |
| 6697927 | Concurrent non-blocking FIFO array A technique for providing concurrent non-blocking access to a circular queue is provided. The concurrent non-blocking circular queue also may be configured such that cache-coherent requesters and a non-cache-coherent requester (e.g., software and hardware... | 02/24/2004 |
| 6694421 | Cache memory bank access prediction A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to... | 02/17/2004 |
| 6690380 | Graphics geometry cache A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) use... | 02/10/2004 |
| 6687803 | Processor architecture and a method of processing A processor architecture including a processor and local memory arrangement where the local memory may be accessed by the processor and other resources at substantially the same time. As a result, the processor may initiate a new or current process follow... | 02/03/2004 |
