Class 711/167 - Access timing

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter including provisions for controlling or coordinating
No. of patents: 2122
Last issue date: 05/07/2013

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Number	Title	Issue Date
7987332	Methods for storing memory operations in a queue A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the ...	07/26/2011
7971021	Systems and methods for managing stalled storage devices Embodiments relate to systems and methods for managing stalled storage devices of a storage system. In one embodiment, a method for managing access to storage devices includes determining that a first storage device, which stores a first resource, is stalled and tra...	06/28/2011
7966468	Apparatus, system, and method for fast read request transfer through clock domains A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous ad...	06/21/2011
7945754	Multiprocessor system, processor, and cache control method A multiprocessor system includes processors each having a primary cache and a secondary cache shared by the processors. The processors each include a read unit that reads data from the primary cache, a request unit that makes a write request when the data to be read...	05/17/2011
7941626	Method and apparatus for controlling discontinuous transmission and reception A method and apparatus for controlling discontinuous transmission and reception are disclosed. A Node-B schedules an offset for discontinuous transmission (DTX) and/or discontinuous reception (DRX) for a user equipment (UE) and sends the offset to the UE. The UE the...	05/10/2011
7934069	Enabling and disabling cache in storage systems Embodiments include methods, apparatus, and systems for enabling and disabling cache in storage systems. One embodiment includes a method that changes a time period for delaying host requests received at a cache of a storage device and converts the storage device fr...	04/26/2011
7934070	Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memor...	04/26/2011
7930507	Method of providing to a processor an estimated completion time of a storage operation A method of performing a storage operation includes: receiving a storage command, estimating the completion time of the associated storage operation, and providing the estimated completion time to a processor. ...	04/19/2011
7925854	System and method of operating memory devices of mixed type A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those m...	04/12/2011
7925855	Method and system for using external storage to amortize CPU cycle utilization A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in g...	04/12/2011
7921271	Hub for supporting high capacity memory subsystem A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access comman...	04/05/2011
7917719	Portable module interface with timeout prevention by dummy blocks Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more compl...	03/29/2011
7908451	Memory command delay balancing in a daisy-chained memory topology A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIM...	03/15/2011
7890729	Memory card and host device thereof A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. ...	02/15/2011
7890728	Memory interface device, memory interface method and modem device A memory interface device has a write detection section that detects the write of a predetermined unit amount of data by a memory write unit into a memory. A signal generation section generates a signal to notify the memory write unit that readout of data from the m...	02/15/2011
7886122	Method and circuit for transmitting a memory clock signal Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock...	02/08/2011
7886123	Memory card and host device thereof A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. ...	02/08/2011
7882322	Early directory access of a double data rate elastic interface A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many ...	02/01/2011
7882323	Scheduling of background scrub commands to reduce high workload memory request latency A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests ...	02/01/2011
7882324	Method and apparatus for synchronizing memory enabled systems with master-slave architecture Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a de...	02/01/2011
7882325	Method and apparatus for a double width load using a single width load port A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-b...	02/01/2011
7870357	Memory system and method for two step memory write operations A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the f...	01/11/2011
7861053	Supporting un-buffered memory modules on a platform configured for registered memory modules A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control...	12/28/2010
7831794	Memory card and host device thereof A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. ...	11/09/2010
7818527	Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory A wrapper circuit effectively converts a muxed-type memory (having time-multiplexed address and data lines) into a non-muxed type memory as seen by the controller (a non-muxed type memory controller). Wrapper circuit includes a select circuit (e.g., multiplexer) and...	10/19/2010
7818528	System and method for asynchronous clock regeneration The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. ...	10/19/2010
7818526	Semiconductor memory device having test mode for data access time A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the dat...	10/19/2010
7818529	Integrated memory control apparatus An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the s...	10/19/2010
7809913	Memory chip for high capacity memory subsystem supporting multiple speed bus A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a ...	10/05/2010
7801933	Storage control system and method A disk array system including a plurality of disk drives, including: a plurality of first-type disk drives being used to form a first-type logical unit having a plurality of a first-type of chunks; a plurality of second-type disk drives being used to form a second-t...	09/21/2010
7793063	Method and system for automatic calibration of a DQS signal in a storage controller A calibration system for a data storage device includes a memory and a memory control module. The memory buffers data between a host and the data storage device and generates a data strobe signal. The memory control module selectively adjusts a delay of the data str...	09/07/2010
7788243	System and methods for optimizing data transfer among various resources in a distributed environment System providing methodology for optimizing data transfer in a distributed environment is described. In one embodiment, for example, in a distributed shared disk cluster environment comprises a plurality of nodes, each node storing database pages in different size b...	08/31/2010
7765376	Apparatuses for synchronous transfer of information Semiconductor devices provide for synchronous transfer of information through a data bus. Address, control and clock information is received, via a command bus and clock line, at a plurality of terminals, the command bus and clock line providing a source synchronous...	07/27/2010
7761682	Memory controller operating in a system with a variable system clock The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perf...	07/20/2010
7757062	Semiconductor integrated circuit apparatus A semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves. In a semiconductor integrated...	07/13/2010
7757061	System and method for decoding commands based on command signals and operating state A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request differen...	07/13/2010
7752410	System and method for accessing data in a multicycle operations cache A hardware implemented method for accessing data in a multicycle operations cache is provided. In this hardware implemented method, a request to access the data in a sub-bank of the multicycle operations cache is received. If the sub-bank is accessed in a previous, ...	07/06/2010
7747832	Method for controlling a memory access The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is...	06/29/2010
7721060	Method and apparatus for maintaining data density for derived clocking Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to mak...	05/18/2010
7721061	Method of predicting response time for storage request An embodiment of a method of predicting response time for a storage request begins with a first step of a computing entity storing a training data set. The training data set comprises past performance observations for past storage requests of a storage array. Each p...	05/18/2010

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Class 711/167 - Access timing