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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 5293611 | Digital signal processor utilizing a multiply-and-add function for digital filter realization A digital signal processor with a built-in dual-port RAM and a bypass signal path for transferring data without the intervention of any bus which is extended between the two ports of the data RAM, whereby in the course of multiply-and-add processing neces... | 03/08/1994 |
| 5276846 | Fast access memory structure A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N ... | 01/04/1994 |
| 5255387 | Method and apparatus for concurrency control of shared data updates and queries Method and apparatus for shared data update and query operations. Two control fields are associated with each data block of interest. Before any data in shared memory is modified, a value different from the present value is written into one of the shared ... | 10/19/1993 |
| 5247687 | Method and apparatus for determining and using program paging characteristics to optimize system productive CPU time Paging data is used to manage address space working set size, system multiprogramming level, and job mix, to improve system productive CPU utilization. System paging characteristics are monitored to determine when to perform management functions. When nee... | 09/21/1993 |
| 5239637 | Digital data management system for maintaining consistency of data in a shadow set A digital data management system for managing a shadow set of storage media includes a plurality of storage media each accessible by at least one data processing device for I/O operations. Successive comparisons are carried out between data stored in corr... | 08/24/1993 |
| 5235687 | Method for replacing memory modules in a data processing system, and data processing system for performing the method The invention relates to the field of data processing systems and provides a method and system to enable replacement of memory modules (MUi) connected to a bus (MB) without interrupting the functioning of the system, wherein for any writing req... | 08/10/1993 |
| 5218698 | Garbage collection system for a symbolic digital processor A memory management process for garbage collection in a symbolic digital processor. An operating processor performs the symbolic digital processing while a memory management processor operates in the background to collect garbage, that is, to discard obso... | 06/08/1993 |
| 5193170 | Methods and apparatus for maintaining cache integrity whenever a CPU write to ROM operation is performed with ROM mapped to RAM Methods and apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM ... | 03/09/1993 |
| 5148523 | Dynamic video RAM incorporationg on chip line modification An architecture for a dynamic video random access memory on a single integrated circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM and further ha... | 09/15/1992 |
| 5148537 | Method and apparatus for effecting an intra-cache data transfer A method and apparatus for effecting a transfer of data between different areas of a memory. Memory reading circuitry and memory writing circuitry are both connected to loopback switching apparatus. The loopback switching apparatus is controllably operabl... | 09/15/1992 |
| 5113370 | Instruction buffer control system using buffer partitions and selective instruction replacement for processing large instruction loops To attain high execution performance of an information processor by improving hit ratio of an instruction buffer in the processor, a part of instructions comprising a loop of the instruction is allocated into the specified area of the instruction buffer a... | 05/12/1992 |
| 5109521 | System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory A personal computer transfers the contents of the computer's slow 16 bit read only memory (ROM) into the computer's fast 32 bit random access memory (RAM), remaps the RAM space to include the ROM space and disables the ROM. Portions of the RAM are tested ... | 04/28/1992 |
| 5079694 | Data processing apparatus having a working memory area A data processing apparatus has a latch circuit between a processing unit and a memory. Processed data produced by the processing unit is not directly written into a working area of the memory, but is temporarily stored in the latch circuit. A write opera... | 01/07/1992 |
| 4771375 | Managing data storage devices connected to a digital computer A storage-management program, executable in one host or simultaneously in a plurality of hosts, manages concurrently executing migration, recall, and recycle (such as defragmentation) tasks. Accesses to data storage volumes (tape, disks, etc.) are managed... | 09/13/1988 |
| 4766535 | High-performance multiple port memory Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 ... | 08/23/1988 |
| 4757469 | Method of addressing a random access memory as a delay line, and signal processing device including such a delay line A random access memory is used to realize a sequence of delay lines (40, 46, 48, 50). The delay lines are linked so that a common end point of two delay lines can be addressed in a read/modify/write operation. Furthermore, the address step between two suc... | 07/12/1988 |
| 4719563 | Data transmission control device for controlling transfer of large amounts of data between two memory units A data transmission control device for controlling the data transfer between two memory means on the basis of an instruction from a processor is disclosed in which the instruction from the processor is decoded, a transfer request is issued to each memory ... | 01/12/1988 |
| 4685088 | High performance memory system utilizing pipelining techniques A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which m... | 08/04/1987 |
| 4636974 | Method and apparatus for transferring data between operationally-juxtaposed memories and knowledge-retrieving systems utilizing same The present invention's fundamental technique for transferring data between two operationally-juxtaposed memories basically entails thress steps: First, a sequential accessing of specified portions of the memories; second, a pair-wise comparison of the ac... | 01/13/1987 |
| 4511962 | Memory control unit A memory control unit for a computer has the function of extracting or synthesizing only a necessary portion from or to two-dimensional image scan data, in addition to a conventional main memory function. It comprises an address controller for calculating... | 04/16/1985 |
| 4463419 | Microprogram control system A microprogram control system for use in a data processor. The system has a plurality of control memories. Under the control of microinstructions stored in one control memory, a necessary microinstruction is loaded from the main memory onto the other cont... | 07/31/1984 |
| 4424562 | Data processing system having plural address arrays In a system including a single main storage or memory and two or more processing units sharing the main storage or memory, there are provided two address arrays for storing the addresses of the data of the main storage or memory which is stored in a buffe... | 01/03/1984 |
| 4187538 | Read request selection system for redundant storage There is provided, in accordance with the present invention, apparatus comprising a shared random access memory in which is stored requests for access to data in a bulk memory unit. The data being stored in redundant storage areas and the requests stored ... | 02/05/1980 |
| 4103334 | Data handling system involving memory-to-memory transfer A device for controlling the handling of data which comprises a main memory for storing a large number of record data items in a state marked off by record-positioning codes, said respective record data items being formed of series-arranged word data item... | 07/25/1978 |
| 4064553 | Information processor An information processor functions to continuously and successively read out from an external memory a plurality of records each consisting of a plurality of words, extract a record whose specified word used as a key word corresponds to the designated con... | 12/20/1977 |
| 4052704 | Apparatus for reordering the sequence of data stored in a serial memory This memory management system provides an improved search logic for locating pages of data stored parallel-by-bit, serially-by-page in a shift register memory and for moving those pages to a position at the head of the file. Searching alternates between f... | 10/04/1977 |
| 3940744 | Self contained program loading apparatus A Read-Only Memory device in the CPU of a microprogrammable computer contains a diagnostic program suitable for self-testing the computer. A microprogram for loading this diagnostic program from the Read-Only Memory device into Main Memory is contained in... | 02/24/1976 |
