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| Number | Title | Issue Date |
| 7136973 | Dual media storage device A dual media storage device is provided. Two separate non-volatile mass storage devices, one having a faster access time and a lower capacity than the other, are combined into a single system. A storage controller can direct the flow of data into one device or the o... | 11/14/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7136958 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 11/14/2006 |
| 7137091 | Hierarchical repeater insertion A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of ... | 11/14/2006 |
| 7133962 | Circulator chain memory command and address bus topology Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line... | 11/07/2006 |
| 7133972 | Memory hub with internal cache and/or memory access prediction A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to ... | 11/07/2006 |
| 7133981 | Prioritized bus request scheduling mechanism for processing devices A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relativ... | 11/07/2006 |
| 7133231 | Method and apparatus for recording data on hard disk drive, and storage medium therefor A method of and an apparatus for recording data on a hard disk drive, and a storage medium containing a program for executing the method. Data is recorded on a track in a recording region and an address of a next track to be recorded with the data is determined so t... | 11/07/2006 |
| 7133991 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 11/07/2006 |
| 7134139 | System and method for authenticating block level cache access on network A data cache for an iSCSI network caches block-level data from WAN servers for use by clients (e.g., LANs). The cache authenticates itself to the WAN servers, and authenticates clients requesting cache access. Mechanisms are provided to prevent clients from accessin... | 11/07/2006 |
| 7130968 | Cache memory architecture and associated microprocessor design A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purp... | 10/31/2006 |
| 7130970 | Dynamic storage device pooling in a computer system A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an... | 10/31/2006 |
| 7127714 | Data transfer request processing scheme for reducing mechanical actions in data storage system There are two classes of scheduling policy: a first class in which a completion of data transfer requested by a data transfer request within a deadline for completing the requested data transfer, specified for the request, is a primary key factor in determining an o... | 10/24/2006 |
| 7127549 | Disk acceleration using first and second storage devices A data storage device is provided. A disk device is combined with a non-volatile memory device to provide much shorter write access time and much higher data write speed than can be achieved with a disk device alone. Interleaving bursts of sector writes between the ... | 10/24/2006 |
| 7127558 | Virtualization controller, access path control method and computer system According to the present invention, it is possible to enhance a performance in accessing a storage system, without performing data migration process between the storages constituting the storage system. A virtualization controller 2 connecting a host computer... | 10/24/2006 |
| 7126784 | Concurrent data recording and reproducing method, seek operation control method and magnetic disk drive using the methods In conventional magnetic disk drives where stream data are treated, seek operations are performed at unnecessarily high speeds. This put the magnetic disk drives at a disadvantage in suppressing noise, reducing power consumption, and lowering the costs of actuator c... | 10/24/2006 |
| 7127573 | Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to th... | 10/24/2006 |
| 7127574 | Method and apparatus for out of order memory scheduling Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into... | 10/24/2006 |
| 7124232 | Bus connection circuit and bus connection system having plural request queues, a bus interface portion outputting request signals, an arbiter performing arbitration of plural requests and a bus interface portion outputting a request signal indicating allocation of pre-fetch buffers corresponding to arbitrated requests A bus connection circuit is connected by a bus to a bridge circuit having a plurality of pre-fetch buffers to access memory. A plurality of request queues and a plurality of request signal outputs and grant signal inputs are provided in a single bus connection devic... | 10/17/2006 |
| 7124252 | Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output... | 10/17/2006 |
| 7124139 | Method and apparatus for managing faults in storage system having job management function A computer system identifies jobs affected by a fault which occurs in any device or mechanism in a storage system to control the execution of such jobs. The computer system includes a DBMS server device, a virtualization switch device, and storage device. Each of th... | 10/17/2006 |
| 7124168 | Per CoS memory partitioning A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also... | 10/17/2006 |
| 7123614 | Method and device for communicating between a first and a second network The invention relates to a method of data-packet transmission from a first network to a second network, one of the networks being a communications bus transporting data packets of isochronous and asynchronous types, characterised in that, with the other network bein... | 10/17/2006 |
| 7124224 | Method and apparatus for shared resource management in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. ... | 10/17/2006 |
| 7120758 | Technique for improving processor performance Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made t... | 10/10/2006 |
| 7120765 | Memory transaction ordering Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that ... | 10/10/2006 |
| 7120756 | Computer system including a promise array A computer system includes a system memory and a plurality of active devices configured to access data associated with the system memory through an address network and a data network. Each of the active devices may be configured to cache data, and may include a prom... | 10/10/2006 |
| 7120723 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 10/10/2006 |
| 7120743 | Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to t... | 10/10/2006 |
| 7120727 | Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr... | 10/10/2006 |
| 7120113 | Systems and methods for limiting low priority traffic from blocking high priority traffic A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated w... | 10/10/2006 |
| 7120715 | Priority arbitration based on current task and MMU A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priori... | 10/10/2006 |
| 7120722 | Using information provided through tag space In some embodiments, the inventions include a device and bus transaction control circuitry to receive bus transactions with tag space including a first part that at times is used to represent a transaction number and a second part that at times contains information ... | 10/10/2006 |
| 7117318 | Memory management A technique for managing an object in memory is disclosed. The technique comprises: assigning the object to an assigned frame wherein the object can be released when the assigned frame is released; detecting an attempt to place a reference to the object in an older ... | 10/03/2006 |
| 7117316 | Memory hub and access method having internal row caching A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the mem... | 10/03/2006 |
| 7114026 | CAM device having multiple index generators A content addressable memory (CAM) device having multiple index generators is described. Each of the index generators is coupled to at least one of a plurality CAM blocks. Each of the plurality of CAM blocks includes a CAM block array and a priority encoder. Each of... | 09/26/2006 |
| 7114029 | Disk drive employing a multi-phase rotational position optimization (RPO) algorithm A disk drive is disclosed which executes a rotational position optimization (RPO) algorithm for selecting a next command to execute out of a plurality of pending commands. The RPO algorithm comprises a first phase and a second phase. The first phase of the RPO algor... | 09/26/2006 |
| 7111123 | Circuit and method to allow searching beyond a designated address of a content addressable memory A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of t... | 09/19/2006 |
| 7107386 | Memory bus arbitration using memory bank readiness A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapa... | 09/12/2006 |
| 7107402 | Packet processor memory interface A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory syst... | 09/12/2006 |
