Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 5432920 | Store control method with hierarchic priority scheme for computer system A store control method for a computer system having a storage with independently accessible plural store banks, plural access request controllers for issuing access requests to the storage, and a store controller for transmitting the access requests to ea... | 07/11/1995 |
| 5428766 | Error detection scheme in a multiprocessor environment An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processo... | 06/27/1995 |
| 5418923 | Circuit for prioritizing outputs of an associative memory with parallel inhibition paths and a compact architecture An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory.... | 05/23/1995 |
| 5394531 | Dynamic storage allocation system for a prioritized cache Methods for managing a Least Recently Used (LRU) cache in a staged storage system on a prioritized basis permitting management of data using multiple cache priorities assigned at the data set level. One method uses the signed difference between an assigne... | 02/28/1995 |
| 5390318 | Managing the fetching and replacement of cache entries associated with a file system Information needed by application programs from a secondary storage is cached in a cache memory which is organized in multiple levels, each level having multiple entries, the entries of each level receiving information of a predetermined category, each en... | 02/14/1995 |
| 5388245 | Memory arbitration method and apparatus for multiple-cycle memory coprocessors employing a data cache unit and stack RAM A memory coprocessor architecture and memory arbitration scheme. The coprocessor architecture includes an address generation unit (AGU), a bus control logic unit (BCL) and a combined data cache unit/stack RAM (DCUSR) unit. Each are connected through a mem... | 02/07/1995 |
| 5383146 | Memory with CAM and RAM partitions A method is described of programming a memory array on a single integrated circuit so that a portion of each data word is characterized as CAM, with the remaining portion of each data word functioning as RAM. The programmable memory array is partitioned i... | 01/17/1995 |
| 5379398 | Method and system for concurrent access during backup copying of data A method and system are disclosed for permitting high concurrency of access during backup copying of designated data stored within a storage subsystem which includes multiple storage devices coupled to the data processing system via a storage subsystem co... | 01/03/1995 |
| 5379379 | Memory control unit with selective execution of queued read and write requests A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing informati... | 01/03/1995 |
| 5369747 | Input/output channel apparatus An input/output channel apparatus includes a channel processing section and plural channel units transfers data between a main memory and peripheral devices in an electronic computer system. The data transfer speed is directly controlled by the data trans... | 11/29/1994 |
| 5367654 | Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry A storage control apparatus of a computer system having a plurality of transfer pipelines issuing access requests to a plurality of memory banks of a storage device. Each memory bank is independently accessible in response to an access instruction from a ... | 11/22/1994 |
| 5265258 | Partial-sized priority encoder circuit having look-ahead capability In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the n... | 11/23/1993 |
| 5247640 | Dual access control system including plural magnetic disk control units and contention control circuitry A dual access control system is disclosed including a write-only memory portion for storing dual access commands issued from a host unit and unit addresses of a magnetic-disk unit, and a contention control portion for receiving coded signals representing ... | 09/21/1993 |
| 5191649 | Multiprocessor computer system with data bus and ordered and out-of-order split data transactions A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first ... | 03/02/1993 |
| 5045997 | Data processor The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver ... | 09/03/1991 |
| 5032984 | Data bank priority system A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generat... | 07/16/1991 |
| 4953079 | Cache memory address modifier for dynamic alteration of cache block fetch sequence A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory conne... | 08/28/1990 |
| 4924425 | Method for immediately writing an operand to a selected word location within a block of a buffer memory A method for controlling a buffer memory for storing a copy of a portion of a main memory, including a step of detecting whether the address in question exists in the buffer memory in response to an instruction to carry out reading from and subsequent wri... | 05/08/1990 |
| 4862411 | Multiple copy data mechanism on synchronous disk drives At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronzied with each other except during the power up phase. The DASD synchronization is controll... | 08/29/1989 |
| 4858107 | Computer device display system using conditionally asynchronous memory accessing by video display controller A computer system has a central processing unit and a video display processor both of which must directly access the system memory. The display processor must access the memory once in a given time period which time period is long enough that several acce... | 08/15/1989 |
| 4703422 | Memory hierarchy control method with replacement based on request frequency In a memory hierarchy system having two or more hierarchy storages of different access speeds and programs and/or data to be loaded on the hierarchy storages, an activity information acquisition unit and a display unit are provided to present information ... | 10/27/1987 |
| 4621318 | Multiprocessor system having mutual exclusion control function A multiprocessor system includes a plurality of processors which are respectively connected to a memory device and each of which produces a first control signal when executing a test-and-set instruction and a second control signal after executing a sequen... | 11/04/1986 |
| 4603383 | Apparatus for direct data transfer among central processing units A data processing system wherein one of a number of central processing units writes a command for data transfer to it from a second processor over a data bus to a common memory and a digital code to an interrupt table, the code indicating interruption of ... | 07/29/1986 |
| 4570221 | Apparatus for sorting data words on the basis of the values of associated parameters Apparatus for quickly sorting a succession of data words on the basis of the value of a specific parameter associated with each data word has a memory divided into M blocks of N storage locations each. A counting device includes a counter for each block, ... | 02/11/1986 |
| 4490782 | I/O Storage controller cache system with prefetch determined by requested record's position within data block In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future... | 12/25/1984 |
| 4402041 | Plural storage areas with different priorities in a processor system separated by processor controlled logic There is disclosed apparatus for keeping two or more distinct groups of data separate from each other within a processor based system. The system employs at least two system areas, where one system area is assigned to have higher priority data than the ot... | 08/30/1983 |
| 4386399 | Data processing system A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. Th... | 05/31/1983 |
| 4151598 | Priority assignment apparatus for use in a memory controller This relates to an apparatus for assigning priority to information temporarily stored in memory controller stack. Associated with each level of the stack is a counter which measures the length of time the information has been stored. A plurality of compar... | 04/24/1979 |
| 4115855 | Buffer memory control device having priority control units for priority processing set blocks and unit blocks in a buffer memory For extracting a unit data block of the lowest priority from a plurality of unit data blocks stored in a buffer memory of large capacity, the unit data blocks are divided into set blocks, each comprising a predetermined number of unit data blocks, and pri... | 09/19/1978 |
| 4115850 | Apparatus for performing auxiliary management functions in an associative memory device Apparatus for managing data and data requests within an associative memory device, wherein the associative memory device is responsive to requests from one or more using devices, such as a digital computer, to store, locate, retrieve, and modify, by means... | 09/19/1978 |
| 4099233 | Electronic data-processing system with data transfer between independently operating miniprocessors A multiplicity of independently operating miniprocessors of an electronic data-processing system are grouped in a number of subsystems each including an individual control unit for carrying out an exchange miniprogram, upon request by an originating minip... | 07/04/1978 |
| 4059850 | Memory system word group priority device with least-recently used criterion A word group priority device for use in a data processing system having a first store and a relatively faster but smaller capacity second store, which device assigns priorities to word groups on a least recently used basis. Upon the read-out or read-in of... | 11/22/1977 |
| 3988717 | General purpose computer or logic chip and system A general purpose logic chip may be replicated for use to construct both the arithmetic unit and the control sections of a computer or other digital data processing or logic circuitry. The chip includes a number of features which when taken together permi... | 10/26/1976 |
| 3949368 | Automatic data priority technique A system for automatically maintaining a record for an order of data priority of data stored in locations of an associative memory which compares the data stored in the locations with newly received data to generate a comparison output and where the order... | 04/06/1976 |
