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| Number | Title | Issue Date |
| 7080219 | Storage controlling device and control method for a storage controlling device A storage controlling device is connected to an external device, where both devices are configured to communicate with each other. The storage controlling device is further configured to execute input/output processes in response to data input/output requests. The i... | 07/18/2006 |
| 7080274 | System architecture and method for synchronization of real-time clocks in a document processing system A system architecture and method are provided for synchronizing the slave clock of one or more resources with the master clock of a controller in a document processing system. The method includes: a) saving a value of the master clock (615); b) generating a d... | 07/18/2006 |
| 7079533 | Systems and methods for bypassing packet lookups A network device determines forwarding information for received data frames. The network device includes input ports, queuing logic, a forwarding engine, and a port filter. The input ports receive data frames. The queuing logic transfers at least some of the receive... | 07/18/2006 |
| 7080188 | Method and system for embedded disk controllers A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and ... | 07/18/2006 |
| 7080194 | Method and system for memory access arbitration for minimizing read/write turnaround penalties A method and system for arbitrating among memory access commands from clients seeking access to a DRAM or other memory, and an arbiter for use in implementing such method or system. When arbitrating among competing commands that include at least one command of the s... | 07/18/2006 |
| 7080218 | Real-time shared disk system for computer clusters A clustered computer system includes a shared data storage system, preferably a virtual shared disk (VSD) memory system, to which the computers in the cluster write data and from which the computers read data, using data access requests. The data access requests can... | 07/18/2006 |
| 7076619 | Storage system and method for reorganizing data to improve prefetch effectiveness and reduce seek distance A method for reorganizing data in a storage device for improved performance is provided where the device stores data as data units each associated with a sequential address. The method for reorganizing data includes allocating a reorganization region capable of stor... | 07/11/2006 |
| 7076745 | Semiconductor integrated circuit device The present invention provides a semiconductor integrated circuit device easy to design timing to be provided with respect to an external memory. In the semiconductor integrated circuit device (10), a second memory controller (16) is provided outside a... | 07/11/2006 |
| 7076626 | Data transfer control device, electronic instrument, and data transfer control method A data transfer control device includes a DMAC1 that writes a packet transferred from a BUS1 (IEEE 1394 or USB), to a SRAM, a DMAC2 that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3 that reads the... | 07/11/2006 |
| 7076636 | Data storage system having an improved memory circuit board configured to run scripts A data storage system includes a set of storage devices, a memory circuit board that includes a cache to temporarily store copies of data elements stored in the set of storage devices, and a processor circuit board that operates as at least one of a front-end interf... | 07/11/2006 |
| 7076593 | Interface bus optimization for overlapping write data Embodiments of the present invention are devices with a queue for receiving a plurality of data write requests and having a means for comparing the data write requests in the queue and then requesting only data identified by the data write requests that would not be... | 07/11/2006 |
| 7073021 | Semantically-aware, dynamic, window-based disc scheduling method and apparatus for better fulfilling application requirements A method for processing requests for information from a disc drive comprising: (a) receiving a plurality of requests, wherein each of the requests has application level information associated with it; (b) identifying a first group of the requests that fit within a t... | 07/04/2006 |
| 7072954 | Network management system having access manager for managing access to recording medium apparatus A network management system is provided in which a transmission band for preceding access is guaranteed even when simultaneous access to shared data is obtained by plural nodes and which does not suffer any problem even in the case of accessing to data that requires... | 07/04/2006 |
| 7073005 | Multiple concurrent dequeue arbiters Plural arbiters arbitrate over a set of queues. The arbiters are constructed as a series of pipelined stages. Conflict detection logic detects conflicts among the arbiters in arbitrating across the queues, and, when a conflict is detected, the conflict detection log... | 07/04/2006 |
| 7072076 | Printing method using PC rendering It is necessary that paper be moved past the printhead at a constant velocity to obtain artifact—free printing. Therefore the printhead requires a constant stream of data during printing. Whilst it is possible to rasterize the page using a page description languag... | 07/04/2006 |
| 7069378 | Multi-bank content addressable memory (CAM) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devi... | 06/27/2006 |
| 7069380 | File access method in storage-device system, and programs for the file access In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the... | 06/27/2006 |
| 7069387 | Optimized cache structure for multi-texturing A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an ind... | 06/27/2006 |
| 7069391 | Method for improved first level cache coherency A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalid... | 06/27/2006 |
| 7069396 | Deferred memory allocation for application threads Various systems and methods are provided that facilitate deferred memory allocation. In one method, an attempt to allocate an amount of memory for an application thread is made. If the attempt was unsuccessful and if the application thread is designated for deferred... | 06/27/2006 |
| 7069399 | Method and related apparatus for reordering access requests used to access main memory of a data processing system A method and related apparatus for reordering access requests used to access main memory of a data processing system. The method includes receiving one or more access requests for accessing the memory device in a first predetermined order, and reordering the access ... | 06/27/2006 |
| 7065596 | Method and apparatus to resolve instruction starvation Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period. ... | 06/20/2006 |
| 7062628 | Method and apparatus for storage pooling and provisioning for journal based storage and recovery A set of interconnected storage systems supporting different types of storage devices and different performance attributes are intelligently applied to process types, such as journal entries. The processes are ranked according to a predetermined priority ranking. St... | 06/13/2006 |
| 7061654 | Image processor, image processing method and storage medium To provide an image processor and an image processing method having enhanced speed of external output to a printer and the like, and a storage medium storing a control program therefor. A time Te(n, k) when the nth image output unit requires image data k is predicte... | 06/13/2006 |
| 7062582 | Method and apparatus for bus arbitration dynamic priority based on waiting period Various approaches grant access to a shared resource. An arbitration circuit includes request shapers that each receive a request from one of the requestors and assign a respective predetermined priority level and age to each of the requests. An arbiter core receive... | 06/13/2006 |
| 7058937 | Methods and systems for integrated scheduling and resource management for a compiler A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are... | 06/06/2006 |
| 7057546 | Binary priority encoder Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130)... | 06/06/2006 |
| 7058952 | Technique for determining an optimal number of tasks in a parallel database loading system with memory constraints A method, apparatus, and article of manufacture of a computer-implemented parallel database loading system. The optimum number of tasks to be processed by the system is determined by identifying the memory constraints of the system, by identifying available processi... | 06/06/2006 |
| 7054249 | Access control apparatus and method for controlling access to storage medium In a write process through channels Ch1, Ch2, and Ch3, the deadline of each channel is set based on the transfer rate variable by the ratio of dummy packets to valid packets, and deadline information is written with write data on a disk. In a re... | 05/30/2006 |
| 7054912 | Data transfer scheme using caching technique for reducing network load In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer d... | 05/30/2006 |
| 7054996 | Method and device for storing and matching arbitrary wide expressions to content addressable memories The present invention relates to a method for storing arbitrarily wide expressions (31) in a set of Content Addressable Memory (CAMs) elements (33) where each CAM element is of lesser width than the expression (31). The CAM element may be a phys... | 05/30/2006 |
| 7054993 | Ternary content addressable memory device A ternary content addressable memory device. The device includes a ternary CAM array segmented into a plurality of array groups, each of which includes a number of rows of ternary CAM cells. Each array group is assigned to a particular priority by storing the priori... | 05/30/2006 |
| 7054971 | Interface between a host and a slave device having a latency greater than the latency of the host An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycle... | 05/30/2006 |
| 7051195 | Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is ma... | 05/23/2006 |
| 7051172 | Memory arbiter with intelligent page gathering logic Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The ar... | 05/23/2006 |
| 7050059 | Method for a graphics chip to access data stored in a system memory of a computer device A method for a graphics chip to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to ... | 05/23/2006 |
| 7051181 | Caching for context switching applications Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage ... | 05/23/2006 |
| 7047489 | Slide show system and method using a browser When a presentation is performed using a web browser, in a manual mode, the display sequence of web pages registered in a bookmark list is specified using an operation button, and in an automatic mode, a plurality of pages registered in a bookmark list are automatic... | 05/16/2006 |
| 7047375 | Memory system and method for two step memory write operations A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation... | 05/16/2006 |
| 7047374 | Memory read/write reordering Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests... | 05/16/2006 |
