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| Number | Title | Issue Date |
| 8108633 | Shared stream memory on multiple processors A method and an apparatus that allocate a stream memory and/or a local memory for a variable in an executable loaded from a host processor to the compute processor according to whether a compute processor supports a storage capability are described. The compute proc... | 01/31/2012 |
| 8069318 | High performance data rate system for flash devices A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic... | 11/29/2011 |
| 8046542 | Fault-tolerant non-volatile integrated circuit memory Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little ex... | 10/25/2011 |
| 8010755 | States encoding in multi-bit flash cells for optimizing error rate To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. W... | 08/30/2011 |
| 8006048 | Signal processing circuit A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external memory based on the first address data and the second address data for pe... | 08/23/2011 |
| 7979648 | Dynamic interleaving Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to increase the number of interleaved physical memory modules when a current int... | 07/12/2011 |
| 7966462 | Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter... | 06/21/2011 |
| 7945746 | Memory sharing of time and frequency de-interleaver for ISDB-T receivers Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of... | 05/17/2011 |
| 7908445 | Redundant controller dynamic logical media unit reassignment A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, the assignment of logical media unit owner can be dynamically reassigned to the receiving storage virtualization... | 03/15/2011 |
| 7904676 | Method and system for achieving varying manners of memory access A method and system for operating a computer system are disclosed. In at least some embodiments, the present invention relates to a method of operating a computer system that includes operating a first cell of the system in accordance with a first memory access conf... | 03/08/2011 |
| 7873800 | Address generator for an interleaver memory and a deinterleaver memory Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a fraction of the address fragments generated, which potentially will excee... | 01/18/2011 |
| 7836263 | Nonvolatile memory controlling method and nonvolatile memory controlling apparatus A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory bank... | 11/16/2010 |
| 7809902 | Method and system for copying DMA with separate strides by a modulo-n counter Provided is a system and method for de-interleaving a data stream stored in a buffer having a plurality of memory locations. Each location has a memory width of (W) bytes and the data stream is formed of a number of data words each including (N) number of data bytes... | 10/05/2010 |
| 7802064 | Flash memory system control scheme A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such ... | 09/21/2010 |
| 7793059 | Interleaving policies for flash memory Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamicall... | 09/07/2010 |
| 7779217 | Systems for optimizing page selection in flash-memory devices A storage device is provided. The storage device includes a memory that includes interleaved fast and slow pages and a controller. In response to a command from a host of the storage device the controller stores fast-reading data in the memory. If the fast and slow ... | 08/17/2010 |
| 7779216 | Method and system of randomizing memory locations A memory system that disperses memory addresses of strings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store strings of data. The CPU is configur... | 08/17/2010 |
| 7779215 | Method and related apparatus for accessing memory A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arra... | 08/17/2010 |
| 7707370 | Information processing apparatus, information processing method, and program An information processing device is provided with a plurality of memory channels, and performs interleave control on a unit memory connected to a memory channel. Furthermore, the information processing device has a circuit for performing the interleave control such ... | 04/27/2010 |
| 7650474 | Method and system for interleaving first and second halves of a data segment of unknown length Method and system for dividing a data segment of unknown length into first and second halves, for example, for interleaving the first and second halves. Units of the data segment are written into first and second register files. With respect to the first register fi... | 01/19/2010 |
| 7620784 | High speed nonvolatile memory device using parallel writing among a plurality of interfaces Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate regions of a single chip. The controller includes logic that processe... | 11/17/2009 |
| 7610457 | Interleaving method and system An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data ... | 10/27/2009 |
| 7552292 | Method of memory space configuration A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of th... | 06/23/2009 |
| 7543121 | Computer system allowing any computer to copy any storage area within a storage system A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas in the storage system. To this end, storage areas provided by the disk... | 06/02/2009 |
| 7493457 | States encoding in multi-bit flash cells for optimizing error rate To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ ... | 02/17/2009 |
| 7461218 | Size-based interleaving in a packet-based link A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory ... | 12/02/2008 |
| 7444460 | Data storage device, method for updating management information in data storage device, and computer program The invention provides a data storage device and a method of updating management information, capable of dealing with management information in a highly reliable manner so that information is not easily lost when an error occurs. File management information such as ... | 10/28/2008 |
| 7433429 | De-interleaver method and system In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer. ... | 10/07/2008 |
| 7424593 | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile m... | 09/09/2008 |
| 7423981 | Method and apparatus for an incremental update of a longest prefix match lookup table A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is pro... | 09/09/2008 |
| 7418571 | Memory interleaving Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels. ... | 08/26/2008 |
| 7415584 | Interleaving input sequences to memory An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency. ... | 08/19/2008 |
| 7404036 | Rebalancing of striped disk data Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set of storage units has been coupled to the controller. The plurality o... | 07/22/2008 |
| 7398362 | Programmable interleaving in multiple-bank memories A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear addres... | 07/08/2008 |
| 7394412 | Unified interleaver/de-interleaver An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector,... | 07/01/2008 |
| 7386691 | Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output dat... | 06/10/2008 |
| 7373453 | Method and apparatus of interleaving memory bank in multi-layer bus system A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals gene... | 05/13/2008 |
| 7370252 | Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory u... | 05/06/2008 |
| 7369135 | Memory management system having a forward progress bit A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a graphics system composed of multiple clients. Pages that are required ... | 05/06/2008 |
| 7366819 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 04/29/2008 |
