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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 5437464 | Data reading and image processing system for CD-ROM A data reading and image processing system for a video entertainment system with a CD-ROM capability is disclosed with a pair of separate computer systems that are controlled through a controller for accessing data from a memory unit. A first computer sys... | 08/01/1995 |
| 5435004 | Computerized system and method for data backup A computerized data backup system and method for dynamically preserving a consistent state of primary data stored in a logical volume of a disk volume management system during processing thereof in a real-time environment. A file system command invokes a ... | 07/18/1995 |
| 5432923 | Memory access control device capable of carrying out data transfer between main memory and expanded memory with simple control In a memory access control device for use in combination with request sources (A, B, C), a main memory (11), and an expanded memory (12), a request receiving port section (13) successively receives a plurality of input requests as received requests. Suppl... | 07/11/1995 |
| 5414829 | Override timing control circuitry and method for terminating program and erase sequences in a flash memory Override control circuitry and a method for terminating a sequence for erasing or programming a computer memory are described. A command register is provided for storing a command sent by an external processor to the memory. A decoder circuit decodes the ... | 05/09/1995 |
| 5414839 | Hybrid lock escalation and de-escalation protocols Requests for memory locks upon nodes in a multi-level resource hierarchy of a computer system are granted and denied by a hybrid escalation/de-escalation protocol that dynamically modifies the resource hierarchy so that lock escalation may restrict the ex... | 05/09/1995 |
| 5388222 | Memory subsystem command input queue having status locations for resolving conflicts Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.... | 02/07/1995 |
| 5388220 | Parallel processing system and data transfer method which reduces bus contention by use of data relays having plurality of buffers A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor elements include a processor, a memory and a data transfer apparatus, all connected to a common bus... | 02/07/1995 |
| 5386525 | System for providing application programs with direct addressability into a shared dataspace A method of sharing dataspaces among a plurality of applications on IBM mainframe computers. A DataServ Routing Table (DSRT) is anchored in an extended command storage area (ECSA) by a pointer stored in a SubSystem Communications vector Table (SSCVT) whic... | 01/31/1995 |
| 5379398 | Method and system for concurrent access during backup copying of data A method and system are disclosed for permitting high concurrency of access during backup copying of designated data stored within a storage subsystem which includes multiple storage devices coupled to the data processing system via a storage subsystem co... | 01/03/1995 |
| 5379395 | Semiconductor integrated circuit for central processor interfacing which enables random and serial access to single port memories A semiconductor integrated circuit serves as an interface between a CPU and the outside enabling communication between systems. More specifically, when a selector is switched to the CPU side, RAMs are accessed at random by the CPU to write data therein, a... | 01/03/1995 |
| 5379443 | Microprocessor providing encoded information on byte enable lines indicating whether reading code or data, location of code/data on data lines, and bit width of code/data A method for signaling the type of access sought by a microprocessor to external memory. A microprocessor can read from or write into external memory. When the microprocessor initiates a read or write cycle, access signals indicating: the read or write cy... | 01/03/1995 |
| 5377344 | Selective memory transaction monitor system A variable value monitoring system and method acquires and displays data information words having addresses within a certain range. In one mode of operation, data information words having addresses within a predetermined range are selected and stored in a... | 12/27/1994 |
| 5375221 | Stand-alone digital data storage control system including user control interface A storage control system includes an apparatus and method for user control of a storage interface to operate a storage medium to store data obtained by a real-time data acquisition system. Digital data received in serial format from the data acquisition s... | 12/20/1994 |
| 5371871 | System for swapping in and out of system memory TSR programs by trapping interrupt calls for TSR and simulating system interrupt A method for the allocation of RAM memory space in a microcomputer environment allows for one or more terminate and stay resident (TSR) or other programs to be stored on a remote memory device in a way that preserves their accessability. The method includ... | 12/06/1994 |
| 5371875 | Logic on main storage memory cards for insertion and extraction of tag bits A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a pointer data word read from the ... | 12/06/1994 |
| 5357615 | Addressing control signal configuration in a computer system A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing... | 10/18/1994 |
| 5355483 | Asynchronous garbage collection The present invention consists of a new type of garbage collector, one that runs in a different process being scanned. With this method, the process being collected communicates its memory state ("a memory snapshot") to a garbage collecting process (GC), ... | 10/11/1994 |
| 5327566 | Stage saving and restoring hardware mechanism A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central processor unit (CPU) with one or more data buses, a set of general purpose registers, instruction... | 07/05/1994 |
| 5325516 | Processor system with dual clock The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing si... | 06/28/1994 |
| 5317712 | Method and apparatus for testing and configuring the width of portions of a memory A circuit and a related process are utilized in a computer system for testing and configuring the width of various portions of memory in a memory array. The circuit captures a state of a memory width control signal (MEMCS16) during a test and configuratio... | 05/31/1994 |
| 5283875 | Method and apparatus for optimizing prefetch caching by reverse ordering of logical blocks Methods and apparatus for optimizing prefetch caching for sets of disc drives with reverse ordered logical block mapping.... | 02/01/1994 |
| 5278960 | Information processing apparatus having detecting means for operand overlaps An information transfer apparatus for transferring memory operand data from a source address in a memory region to a destination address, including a first and second data overlap detecting circuits. If either detecting circuit indicates that data overlap... | 01/11/1994 |
| 5235688 | Memory access control unit for allowing maximum throughput of an I/O processor and an I/O request buffer full state When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from th... | 08/10/1993 |
| 5226139 | Semiconductor memory device with a built-in cache memory and operating method thereof A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of colu... | 07/06/1993 |
| 5204967 | Sorting system using cascaded modules with levels of memory cells among which levels data are displaced along ordered path indicated by pointers A self-sorting memory system (SSM) in which records to be sorted are stored in selected memory cells in random access memories. The system is constructed so that the amount of time required to sort the records depends only on the number of records to be s... | 04/20/1993 |
| 5201043 | System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking A microprocessor which includes means for detecting misaligned data reference is described. The detecting means is selectable such that when it is enabled and reference is made to a misaligned data object, a fault is produced which interrupts the currentl... | 04/06/1993 |
| 5179679 | Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss A microprocessor is described which includes on a single substrate a central processing unit (CPU), write buffer and cache memory. The write buffer includes storage in each of its sections for a bit which indicates a hit/miss condition for the write cycle... | 01/12/1993 |
| 5175838 | Memory circuit formed on integrated circuit device and having programmable function A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycl... | 12/29/1992 |
| 5170474 | Method of searching a queue in response to a search instruction A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search... | 12/08/1992 |
| 5093785 | Portable electronic device with memory having data pointers and circuitry for determining whether a next unwritten memory location exist A portable electronic device in which when data is written in a PROM the start address of the next unwritten area is stored in a RAM incorporated in a CPU of the portable electronic device. A data memory is divided into a plurality of areas, and each area... | 03/03/1992 |
| 5051890 | Program/data memory employed in microcomputer system A semiconductor memory unit employed in a microcomputer system includes an address counter for fetching address information from a microcomputer in response to an address latch signal from the microcomputer. The address counter further receives an updatin... | 09/24/1991 |
| 4980853 | Bit blitter with narrow shift register The present invention provides a fast bit blitter method and circuit which uses less logic than do prior art bit blitter circuits. A circuit built in accordance with the present invention includes four main components each of which only has as many bit po... | 12/25/1990 |
| 4926314 | Method and apparatus for determining available memory size The present invention provides an apparatus and method for use in a computer system, and particularly, a computer system employing memory devices having discrete capacity (i.e., 256K bit, 1M bit, etc.), such as random access memory (RAM). The present inve... | 05/15/1990 |
| 4903299 | ID protected memory with a maskable ID template A remotely disposed RAM (12) is provided which is accessible by a centralized serial CPU (28) through a common data link. The RAM (12l ) is interfaced with the common data link through a serial port (19) and access thereto is controlled by an arbiter (10)... | 02/20/1990 |
| 4894797 | FIFO data storage system using PLA controlled multiplexer for concurrent reading and writing of registers by different controllers A first-in-first out (FIFO) register 100 for storage of up to two-bytes of data is operable by two control units 10, 20 for simultaneous read and write operations with no wait states. The FIFO register 100 comprises a first register 101, a second register... | 01/16/1990 |
| 4868781 | Memory circuit for graphic images A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and... | 09/19/1989 |
| 4835738 | Register stack for a bit slice processor microsequencer A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the regis... | 05/30/1989 |
| 4796222 | Memory structure for nonsequential storage of block bytes in multi-bit chips A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a c... | 01/03/1989 |
| 4747039 | Apparatus and method for utilizing an auxiliary data memory unit in a data processing system having separate program and data memory units In a data processing system in which the program memory unit and the internal data memory unit are separately addressed, and which special instructions for transferring data between these two units are available, apparatus and method are described for inc... | 05/24/1988 |
| 4734851 | Write protect control circuit for computer hard disc systems A write protect system prevents inadvertent attempts to write data into a permanent memory storage device (such as a disc drive) containing valuable data that might be destroyed by such a write attempt. The write protect system includes a controller coupl... | 03/29/1988 |
