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| Number | Title | Issue Date |
| 7493455 | Memory writing device for an electronic device To provide a memory-writing device which can simply and reliably write desired data to a nonvolatile memory of an electronic device, connection is made with an ECU to perform write processing to write write data from the memory-writing device to a flash ROM by copyi... | 02/17/2009 |
| 7490204 | Using constraints to simplify a memory controller A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) inco... | 02/10/2009 |
| 7487304 | Packet processor memory interface with active packet list A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which processing has completed respectively. Upon receiving a packet start comman... | 02/03/2009 |
| 7487301 | Method and system for accelerated access to a memory Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating ... | 02/03/2009 |
| 7487302 | Service layer architecture for memory access system and method A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second con... | 02/03/2009 |
| 7487303 | Flash memory device and associated data merge method A memory system comprises a flash memory and a controller comprising a control logic circuit and a working memory storing a flash translation layer. The memory system performs a merge operation by selectively copying a page from a first block of the flash memory to ... | 02/03/2009 |
| 7484054 | System and method for performing storage operations in a computer network Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage ... | 01/27/2009 |
| 7484053 | Cross-referencing cache line addresses with corresponding names An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels. The caches comprise a plurality of cache line addresses, each cache line address associated with ... | 01/27/2009 |
| 7484051 | Apparatus, system and method for reliably updating a data group in a read-before-write data replication environment using a comparison file An apparatus, system, and method are disclosed for reliably updating a data group in a data replication environment. The apparatus, system, and method reliably update the data group by receiving an updated data group sent from a first storage medium to a second stor... | 01/27/2009 |
| 7484052 | Distributed address arbitration scheme for symmetrical multiprocessor system The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function ther... | 01/27/2009 |
| 7484050 | High-density storage systems using hierarchical interconnect A system and method for coupling a host to a drive in a high-capacity data storage system are disclosed. The data storage system comprises a number of drives arranged in a hierarchical manner. A control system is provided for controlling input/output of data and man... | 01/27/2009 |
| 7484049 | Data storage system packer/depacker A system for aggregating portions of multiple blocks of data into a single composite block. The block of data comprises different packets of data stored in correspondingly different sections of a memory. The system gathers selected portions of the stored packets and... | 01/27/2009 |
| 7480774 | Method for performing a command cancel function in a DRAM A method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device to improve reliability and speed of a memory system. The CC function rakes advantage of the intrinsic delays associated wit memory read operations at ... | 01/20/2009 |
| 7480775 | Method and apparatus for block-oriented memory management provided in smart card controllers A method for memory management in smart card controllers by writing of data into a data space in a persistent memory is described. In order to save memory space the persistent memory is split into blocks with fixed data length having logical block numbers; whereby t... | 01/20/2009 |
| 7480776 | Circuits and methods for providing variable data I/O width for semiconductor memory devices Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fl... | 01/20/2009 |
| 7478209 | Packet processor memory interface with conflict detection and checkpoint repair A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and ... | 01/13/2009 |
| 7478208 | Semiconductor memory devices including mode registers and systems including the same Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plural... | 01/13/2009 |
| 7478206 | Information-processor for controlling a storing area in accordance with an amount of requested information A storing/reproducing device includes a storing controller that recognizes programming information read out from timer recording list information and the data size of a content corresponding to the programming information, and compares the data size with free spaces... | 01/13/2009 |
| 7478207 | Control system with a write filter for protection of data A control system configured to control a predetermined unit by using a control program running on a general-purpose OS. The control system includes an auxiliary storage device configured to store the general-purpose OS, the control program, and various data items re... | 01/13/2009 |
| 7475201 | Packet processor memory interface with conditional delayed restart A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and ... | 01/06/2009 |
| 7475199 | Scalable network file system An incrementally-scalable file system and method. The system architecture enables file systems to be scaled by adding resources, such as additional filers and/or file servers, without requiring that the system be taken offline or being known to client applications. ... | 01/06/2009 |
| 7475200 | Packet processor memory interface with write dependency list A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and ... | 01/06/2009 |
| 7469323 | Hosting service platform system and method A computer cluster for providing hosting services includes a plurality of nodes, and a control center coordinating activity of the nodes. Each node includes a plurality of virtual environments such that each virtual environment responds to user requests and appears ... | 12/23/2008 |
| 7467263 | Storage system, management apparatus & method for determining a performance problem using past & current performance values of the resources A highly-reliable system, a management apparatus and method that can enhance the reliability of a storage system is provided. The present invention provides a storage system having a higher level system with a predetermined application installed, a storage ap... | 12/16/2008 |
| 7464230 | Memory controlling method A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a c... | 12/09/2008 |
| 7464229 | Serial-write, random-access read, memory A serial-write, random-access read, memory addresses applications where the data in the memory may change more frequently than would make a PROM suitable, but that changes much less frequently than would require a RAM. This enables the circuit designer to optimize t... | 12/09/2008 |
| 7461216 | Memory controller A memory controller for accessing a memory module comprising a plurality of memory banks. The memory controller is operable to write copies of program data to one or more memory banks according to the size of the program data. The memory controller is additionally o... | 12/02/2008 |
| 7461215 | Advanced processor with implementation of memory ordering on a ring based data movement network An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 12/02/2008 |
| 7461217 | Arrangement and method for update of configuration cache data An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique. This provides the advantage that known changes to the subsystem do not re... | 12/02/2008 |
| 7457925 | Storage control method and system To enable favorable control of the storage of electronic information, a management device connected communicably to one or more storage control devices that are connected communicably to at least one of a plurality of storage devices refers to resource information r... | 11/25/2008 |
| 7451281 | System and method for using swappable storage for storing program data One embodiment provides a method of providing a user with information quicker than could be achieved by obtaining the information from a storage source, the method comprising receiving a request from a user for stored data accessible by the user, the stored data mai... | 11/11/2008 |
| 7447847 | Memory device trims Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim cir... | 11/04/2008 |
| 7447848 | Memory device row and/or column access efficiency Embodiments for retrieving data from memory devices using sub-partitioned addresses are disclosed. ... | 11/04/2008 |
| 7447849 | Memory controller configuration system and method A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers. ... | 11/04/2008 |
| 7444493 | Address translation for input/output devices using hierarchical translation tables An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to... | 10/28/2008 |
| 7444485 | Method and apparatus for duplicating computer backup data Method and apparatus for performing logical duplication of backup data in a computer system including a host computer, a storage device storing data for the host computer, and at least one computer-readable backup storage medium storing backup data copied from the s... | 10/28/2008 |
| 7444492 | Processor, virtual memory system, and virtual storing method A processor includes an address specifying unit that specifies an address range on a virtual storage area; an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range; a calculating unit ... | 10/28/2008 |
| 7444482 | Storage pools with write atomicity A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device ... | 10/28/2008 |
| 7444480 | Processor, memory device, computer system, and method for transferring data A processor connected to a memory device includes a random number generator that generates random numbers identical to random numbers generated in the memory device; an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory d... | 10/28/2008 |
| 7444481 | Packet processor memory interface with memory conflict valve checking A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based u... | 10/28/2008 |
