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| Number | Title | Issue Date |
| 7265865 | Security for mass storage devices in imaging devices Imaging devices can have mass storage devices associated with them. In a networked environment that allows mounting of a shared resource, these mass storage devices can be viewed or even altered by anyone who can connect to the imaging device. However, unrestricted ... | 09/04/2007 |
| 7263592 | Method for completely lock-free user-level dynamic memory allocation The present invention relates to a method, computer program product and system for a general purpose dynamic memory allocator that is completely lock-free, and immune to deadlock, even when presented with the possibility of arbitrary thread failures and regardless o... | 08/28/2007 |
| 7263524 | Data access methods and multifunction device therefor Data access methods and multifunction device therefor. The invention is preferably embodied in computer-readable media operatively associated with a multifunction device and having computer-readable program code thereon. The computer-readable program code may compri... | 08/28/2007 |
| 7260677 | Programmable system and method for accessing a shared memory A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more addit... | 08/21/2007 |
| 7260685 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 08/21/2007 |
| 7260688 | Method and apparatus for controlling access to memory circuitry Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality... | 08/21/2007 |
| 7260689 | Methods and apparatus for detecting use of common resources Historical access information identifies which resources in a storage area network access portions of shared storage in the storage area network. Based on an analysis of the historical access information, a management report generator application analyzing such info... | 08/21/2007 |
| 7260668 | Network co-processor for vehicles A network processor exchanges data of various descriptions via a plurality of network nodes with external network devices, such as other processors, controllers, transducers, or sensors. The network processor includes a master processor for control tasks of the proc... | 08/21/2007 |
| 7260613 | Storage system, disk control cluster including channel interface units, disk interface units, local shared memory units, and connection portions, and a method of increasing of disk control cluster In a storage system in which: LSW 110 is a local switch, GSW 115 is a global switch, and 21 is a global shared memory unit; when a host computer 3 makes a data read request to a disk control cluster 1-1, a channel interface ... | 08/21/2007 |
| 7257705 | Method for preserving changes made during a migration of a system's configuration to a second configuration Techniques for reconfiguring systems that are configured by modifying configuration tables in a database. Reconfiguration begins by making a copy of the production version to obtain the development version and a snapshot showing the current state of the configuratio... | 08/14/2007 |
| 7257694 | Method for allocating storage area to virtual volume In a system where a storage device is coupled to a computer, a storage area in the storage device is efficiently allocated to the computer. The system comprises a virtualization apparatus to be coupled to the virtulization apparatus. The virtualization apparatus, re... | 08/14/2007 |
| 7256790 | Video and graphics system with MPEG specific data transfer commands A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing t... | 08/14/2007 |
| 7257683 | Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read respo... | 08/14/2007 |
| 7257091 | Controlling the state of duplexing of coupling facility structures A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on ... | 08/14/2007 |
| 7257680 | Storage system including shared memory and plural disk drives, processors, and shared memory control units A storage system coupled to host computers, includes: a plurality of disk drives; a plurality of processors, each controlling data reception and data transmission between the host computers and the disk drives; a shared memory for storing control information; and a ... | 08/14/2007 |
| 7257582 | Load balancing with shared data The input of a computer executable process, is logically subdivided, without reading, into a plurality of partitions which are distributed to a plurality of processors in which respective subtasks including the reading of those partitions, are carried out. The metho... | 08/14/2007 |
| 7257674 | Raid overlapping A first array of disk drives overlaps with a second array of disk drives in a Redundant Array of Inexpensive Drives (RAID) system, in which the first and second arrays share at least one disk drive. A first stripe of data from a first client is stored in the first a... | 08/14/2007 |
| 7257685 | Memory management Improving performance of a computer program is disclosed. A first set of escape data is gathered. A first compiled program is provided using the first set of escape data. A second set of escape data is gathered based on the first compiled program. A second compiled ... | 08/14/2007 |
| 7254679 | Computer system for data processing and method for the transfer of an array segment of an affine-indexed multi-dimensional array referenced in a loop nest from a first memory to a second memory Computer system for electronic data processing having programmable data transfer units used for transferring data from a first memory in which data is stored in a form of a multi-dimensional array to a second memory in such a way, that spatial or temporal locality f... | 08/07/2007 |
| 7254687 | Memory controller that tracks queue operations to detect race conditions A technique for controlling access to resources that may be accessed by one or more entities in a system. According to the technique, an entity accesses a shared resource by issuing a request containing an identifier that identifies the resource and an operation tha... | 08/07/2007 |
| 7254674 | Distribution of I/O requests across multiple disk units A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical... | 08/07/2007 |
| 7254670 | System, method, and apparatus for realizing quicker access of an element in a data structure This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shif... | 08/07/2007 |
| 7254607 | Dynamic coordination and control of network connected devices for large-scale network site testing and associated architectures Dynamic coordination and control of network connected devices within a distributed processing platform is disclosed for large-scale network site testing, or for other distributed projects. For network site testing, the distributed processing system utilizes a plural... | 08/07/2007 |
| 7254331 | System and method for multiple bit optical data transmission in memory systems The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of light so that each pulse of optical signals can represent more than a single bit of data. An optical tran... | 08/07/2007 |
| 7254688 | Data processing apparatus that shares a single semiconductor memory circuit among multiple data processing units Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or 202-2) ending control of a semiconductor memory... | 08/07/2007 |
| 7251815 | Multiple virtual machines sharing processor and work queue in memory having program/dispatch functions for assigning and accessing work items while the virtual machine was not idle A system, computer program product and method for dispatching work items in a virtual machine operating system. The virtual machine operating system defines first and second virtual machines. First and second work queues are created in a memory. The first virtual ma... | 07/31/2007 |
| 7251660 | Providing mappings between logical time values and real time values in a multinode system Techniques are provided for providing mappings between logical time values and real time values in a multinode system. The techniques include, if a first event occurs, then writing an LTV-to-RTV mapping to a non-volatile data structure. If a second event occurs, the... | 07/31/2007 |
| 7251714 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 07/31/2007 |
| 7251744 | Memory check architecture and method for a multiprocessor computer system Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wh... | 07/31/2007 |
| 7251822 | System and methods providing enhanced security model The present invention relates to a system and methodology to facilitate security for data items residing within (or associated with) a hierarchical database or storage structure. A database security system is provided having a hierarchical data structure associated ... | 07/31/2007 |
| 7249220 | Storage system To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnectio... | 07/24/2007 |
| 7249226 | Semiconductor system and memory sharing method A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address, and which uses the shared memory; an address allocation unit which allo... | 07/24/2007 |
| 7249236 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 07/24/2007 |
| 7245145 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/17/2007 |
| 7246182 | Non-blocking concurrent queues with direct node access by threads Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue... | 07/17/2007 |
| 7246218 | Systems for increasing register addressing space in instruction-width limited processors A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommod... | 07/17/2007 |
| 7243131 | Information processing system using remote control, with device and method therefor A personal computer that is a controller transmits a reserve request for reserving a remote control. An MD recorder/player that is a target sets a reserve mode corresponding to the reserve request. The MD recorder/player prohibits another controller from performing ... | 07/10/2007 |
| 7243229 | Exclusive access control apparatus and method A computing system and an exclusive access control method are provided for preventing degraded performance of a network caused by exclusive access control, and for permitting a computer to exclusively access a storage area irrespective of whether a storage has an ex... | 07/10/2007 |
| 7242213 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/10/2007 |
| 7243179 | On-chip inter-subsystem communication A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the ... | 07/10/2007 |
