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| Number | Title | Issue Date |
| 4751638 | Buffer storage control system having buffer storage unit comparing operand (OP) side and instruction fetch (IF) side tag storages A buffer storage control system is incorporated in a multiprocessor and includes therein operand side buffer storages and instruction fetch side buffer storages. Under control of the system, a store operation is achieved with the use of an identification ... | 06/14/1988 |
| 4736336 | Asynchronous demand selector with multi-tape delay line A data processor asynchronous demand selector includes a time selector for selecting an asynchronous demand according to the time it is applied to the selector. A spatial selector controls each demand selected by the time selector according to a predeterm... | 04/05/1988 |
| 4729091 | Directing storage requests prior to address comparator initialization with a reference address range An apparatus directs storage requests from a processor through a storage controller to storage. The storage controller contains address comparators which are uninitialized, i.e., they contain no address identifiers. As a result, logic within the storage c... | 03/01/1988 |
| 4722048 | Microcomputer system with independent operating systems A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer syste... | 01/26/1988 |
| 4707781 | Shared memory computer method and apparatus A shared memory computer method and apparatus having a plurality of sources, a memory manager, and memory units in which the memory locations of data items are randomly distributed. The memory manager includes a translation module for locating data items ... | 11/17/1987 |
| 4698753 | Multiprocessor interface device A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbit... | 10/06/1987 |
| 4675811 | Multi-processor system with hierarchy buffer storages A multi-processor system includes a main storage and buffer storages of multi-layered hierarchy, which share the main storage. A plurality of storage controllers, each of which contains a first buffer storage, are connected with the main storage and at le... | 06/23/1987 |
| 4658356 | Control system for updating a change bit Change bits are provided in correspondence with storage information units (blocks or pages) of a storage, and indicate whether or not a "store" operation has been performed into the corresponding storage information units. The change bits are retained in ... | 04/14/1987 |
| 4656579 | Digital data processing system having a uniquely organized memory system and means for storing and accessing information therein A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedu... | 04/07/1987 |
| 4654779 | Multiprocessor system including firmware A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units and a main memory to be commonly occupied by all the central processing units. The main memory is composed of an operating system are... | 03/31/1987 |
| 4642755 | Shared memory with two distinct addressing structures A communication method and digital multi-customer data interface for interconnecting a number of customer terminals to a main packet switching network of a local area data transport system that provides data communication services such as interactive vide... | 02/10/1987 |
| 4628482 | Common memory control system with two bus masters In accordance with the present invention, there is provided a data processing apparatus comprising an MPU which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means for latching said address signal, a memory wh... | 12/09/1986 |
| 4600990 | Apparatus for suspending a reserve operation in a disk drive Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the ... | 07/15/1986 |
| 4564903 | Partitioned multiprocessor programming system The disclosure provides a unique multiprocessing (MP) method for executing on plural CPUs of the MP a uniprocessor system (UPS) program not written to run on a MP system. Separate copies of the UPS are provided in the shared main storage (MS) of the MP. A... | 01/14/1986 |
| 4494215 | Disk system A disk system comprising a plurality of disk units (1-0 to 1-7) divided into primary logical volumes (101 to 171) and secondary logical volumes (102 to 172) which are controlled by a plurality of disk controllers (4-AA to 4-BB). One of disk controllers se... | 01/15/1985 |
| 4491909 | Data processing system having shared memory In a data processing system, data is transferred between a plurality of functional devices through a shared memory without the intervention of the processor. The data transfer is controlled by a Shared Memory Access Channel (SMAC) having a pointer table s... | 01/01/1985 |
| 4410944 | Apparatus and method for maintaining cache memory integrity in a shared memory environment A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor ... | 10/18/1983 |
| 4410946 | Cache extension to processor local storage The disclosure pertains to a relatively small local storage (LS) in a processor's IE which can be effectively expanded by utilizing a portion of a processor's store-in-cache. The cache allocates a line (i.e. block) for LS use by the instruction unit sendi... | 10/18/1983 |
| 4394734 | Programmable peripheral processing controller A peripheral processing controller controls access to a peripheral memory by specialized peripheral devices. The specialized peripheral devices process all of the data independently of a central processor that simply supervises the system. The controller ... | 07/19/1983 |
| 4345309 | Relating to cached multiprocessor system with pipeline timing A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds t... | 08/17/1982 |
| 4334285 | Divider for calculating by summation the quotient and remainder of an integer divided by a Mersenne number and a parallel processor system comprising memory modules, a Mersenne prime in number For division by a Mersenne number (2n -1), a divided P is expressed as: ##EQU1## A first summing unit sums up the coefficients ai 's to provide a sum of a carry multiplied by 2n and a sum portion less than 2n. | 06/08/1982 |
| 4295219 | Memory write error detection circuit A circuit for the detection of write errors in a memory with selectable byte addressing. The memory is capable of selectively writing bytes within a memory word by decoding control signals and address signals received from a processor. The decoder and tra... | 10/13/1981 |
| 4253146 | Module for coupling computer-processors A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules... | 02/24/1981 |
| 4253144 | Multi-processor communication network A network is described wherein a plurality of processors are connected in a hierarchy of levels with provision for communication between the various processors. A Global Memory Module (GMM) and a system hierarchy of processors is described which provides ... | 02/24/1981 |
| 4212076 | Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former A digital computer of relatively simple and efficient structural organization which is capable not only of conventional arithmetic operations according to a program but also of (i) performing chained Boolean logic processing on any selected bit of any of ... | 07/08/1980 |
| 4187538 | Read request selection system for redundant storage There is provided, in accordance with the present invention, apparatus comprising a shared random access memory in which is stored requests for access to data in a bulk memory unit. The data being stored in redundant storage areas and the requests stored ... | 02/05/1980 |
| 4153934 | Multiplex data processing system The multiplex data processing system comprises a plurality of data processing units connected to form a non-hierachical structure, a shared memory device commonly used by the plurality of data processing units and a job registration unit accessable to the... | 05/08/1979 |
| 4110823 | Soft display word processing system with multiple autonomous processors A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous... | 08/29/1978 |
| 4073005 | Multi-processor computer system Two or more processors share a large main memory in which are stored the programs and data sets on which the processors operate. Each processor operates independently from every other one, and selects its tasks for operation on the basis of information co... | 02/07/1978 |
| 4056844 | Memory control system using plural buffer address arrays In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by... | 11/01/1977 |
