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| Number | Title | Issue Date |
| 8185702 | Multimedia platform A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a r... | 05/22/2012 |
| 8185701 | System and method for an adaptive list prefetch A method, system, and computer program product are provided for retrieving records into a main memory. A first number of gaps and a first total gap size are received for a list of records from a database subsystem. A determination is made of a first average gap size... | 05/22/2012 |
| 8180972 | Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally, the hybrid computing environment including a host computer and a plurality of accelerators, the host computer and the accelerators each having local memory... | 05/15/2012 |
| 8180973 | Servicing interrupts and scheduling code thread execution in a multi-CPU network file server Interrupts and code threads are assigned in a particular way to the core CPUs of a network file server in order to reduce latency for processing client requests for file access. Threads of the network stack are incorporated into real time threads that are scheduled ... | 05/15/2012 |
| 8180974 | System, apparatus, and method for modifying the order of memory accesses Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines... | 05/15/2012 |
| 8176264 | Software transactional memory for dynamically sizable shared data structures We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock... | 05/08/2012 |
| 8176263 | Memory management apparatus and method for same A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided f... | 05/08/2012 |
| 8171232 | Stored value accessors in shared memory regions Instruction sets in computing environments may execute within one of several domains, such as a natively executing domain, an interpretively executing domain, and a debugging executing domain. These domains may store values in a shared region of memory in different ... | 05/01/2012 |
| 8171233 | Multi port semiconductor memory device with direct access function in shared structure of nonvolatile memory and multi processor system thereof A multiport semiconductor memory device and a multiprocessor system employing the same directly accesses a shared nonvolatile memory. The multiport semiconductor memory device includes a plurality of port units coupled with respective corresponding processors. A sha... | 05/01/2012 |
| 8166253 | Memory management system in a computer system with shared memory mappings A memory management sub-system includes code executable by a processor fir performing selecting a plurality of contexts, and selecting a sample of the separately allocable portions of an address space for each of the contexts. For each of the selected allocable port... | 04/24/2012 |
| 8156289 | Hardware support for work queue management The claimed matter provides systems and/or methods that effectuate utilization of fine-grained concurrency in parallel processing and efficient management of established memory structures. The system can include devices that establish memory structures associated wi... | 04/10/2012 |
| 8145850 | Method and system for visualizing a storage area network A method and system for visualizing a SAN is disclosed. In one embodiment, a method for visualizing a SAN includes scanning SAN components in the SAN to determine respective types of the SAN components and connectivity information between the SAN components. The met... | 03/27/2012 |
| 8135918 | Data de-duplication for iSCSI Redundant data is identified and eliminated in a network that implements the iSCSI protocol either in-band at the source, in-band at the target, or out-of-band at the target. For in-band de-duplication, a data block included with a write command is assigned a unique... | 03/13/2012 |
| 8127086 | Transparent hypervisor pinning of critical memory areas in a shared memory partition data processing system Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical m... | 02/28/2012 |
| 8122198 | Modified machine architecture with partial memory updating The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Mem... | 02/21/2012 |
| 8117402 | Decreasing shared memory data corruption The shared memory includes a header section and a data section, wherein said header section includes at least two headers in which control information is stored. The method comprises the steps of: judging whether or not there is data corruption in one of said at lea... | 02/14/2012 |
| 8095741 | Transactional memory computing system with support for chained transactions A computing system processes memory transactions for parallel processing of multiple threads of execution provides execution of multiple atomic instruction groups (AIGs) on multiple systems to support a single large transaction that requires operations on multiple t... | 01/10/2012 |
| 8095742 | Microcomputer with address translation circuit A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the me... | 01/10/2012 |
| 8095743 | Memory access control in a multiprocessor system Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first p... | 01/10/2012 |
| 8095740 | Method and apparatus for accessing data of a message memory of a communication module A method and an apparatus for accessing data of a message memory of a communication module by inputting or outputting data into or from the message memory, the message memory being connected to a buffer memory assemblage and the data being transferred to the message... | 01/10/2012 |
| 8082400 | Partitioning a memory pool among plural computing nodes To share a memory pool that includes at least one physical memory in at least one of plural computing nodes of a system, firmware in management infrastructure of the system is used to partition the memory pool into memory spaces allocated to corresponding ones of at... | 12/20/2011 |
| 8078575 | Disaster recovery File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that fa... | 12/13/2011 |
| 8074030 | Using transactional memory with early release to implement non-blocking dynamic-sized data structure By exploiting an early release facility that may be provided by certain transactional memory designs, we facilitate transaction software constructs that operate on dynamically-sized data structures and/or other data structures for which traversal may be data depende... | 12/06/2011 |
| 8069314 | Shared memory architecture in GPS signal processing A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within t... | 11/29/2011 |
| 8060703 | Techniques for allocating/reducing storage required for one or more virtual machines Techniques for allocating/reducing storage required for one or more virtual machines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for allocating storage for one or more virtual machines. The method may comprise pr... | 11/15/2011 |
| 8055852 | Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing function... | 11/08/2011 |
| 8055853 | Data storage system and data storage program for atomic transactions Atomic data are stored in blocks on a hard disk. The blocks are grouped into a committed block aggregate P1, which exists only on the hard disk, a next-generation committed block aggregate C1, which is converted into a committed block aggregate at pred... | 11/08/2011 |
| 8046540 | Shared closures on demand A method and apparatus for copying data from a virtual machine to a shared closure on demand. This process improves system efficiency by avoiding the copying of data in the large number of cases where the same virtual machine is the next to request access and use of... | 10/25/2011 |
| 8032718 | Systems and methods for sharing media in a computer network A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy cop... | 10/04/2011 |
| 8024528 | Global address space management Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. Th... | 09/20/2011 |
| 8015368 | Processor extensions for accelerating spectral band replication Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other aud... | 09/06/2011 |
| 8015367 | Memory management methods in a computer system with shared memory mappings A host computer system is configured to present each of multiple resident contexts with an address space that may be mapped, at least in part, to corresponding portions of a host memory. The address space of a selected context is sampled, and, for each of a pluralit... | 09/06/2011 |
| 8010751 | Data forwarding engine A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of... | 08/30/2011 |
| 8001333 | Memory management in a shared memory system Methods, systems and computer program products to maintain cache coherency, in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response ... | 08/16/2011 |
| 7996628 | Cross adapter shared address translation tables A method, computer program product and computer system for allocating shared address translation tables for memory regions of multiple I/O adaptors, which includes allocating an address translation table to be shared between the memory regions, creating a hardware c... | 08/09/2011 |
| 7996627 | Replication of object graphs The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Obj... | 08/09/2011 |
| 7996630 | Method of managing memory in multiprocessor system on chip Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a va... | 08/09/2011 |
| 7996629 | Multiprocessor computing system with multi-mode memory consistency protection Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors... | 08/09/2011 |
| 7990315 | Shared memory device applied to functional stages configured in a receiver system for processing signals from different transmitter systems and method thereof A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system ... | 08/02/2011 |
| 7984246 | Multicore memory management system A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directl... | 07/19/2011 |
