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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 7076614 | System and method for optimizing bus bandwidth utilization by grouping cache write-backs A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at lea... | 07/11/2006 |
| 7075857 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/11/2006 |
| 7073043 | Multiprocessor system supporting multiple outstanding TLBI operations per partition Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unloc... | 07/04/2006 |
| 7072350 | Polling response selection using request monitoring in a network switch apparatus A switch node includes arbiter logic configured to gather global information regarding switching requests within the switch node and to control switching of one or more packets through the switch node. The arbiter logic may include a bus snooping interface configure... | 07/04/2006 |
| 7073026 | Microprocessor including cache memory supporting multiple accesses per cycle A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes... | 07/04/2006 |
| 7073030 | Method and apparatus providing non level one information caching using prefetch to increase a hit ratio A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache li... | 07/04/2006 |
| 7073044 | Method and apparatus for sharing TLB entries A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may ... | 07/04/2006 |
| 7069362 | Topology for shared memory computer system A dual ring topology for multiprocessing computer systems. The dual ring topology interconnects multiple building blocks (nodes) to each other, each node comprising processing elements, memory and IO devices. The topology allows for the dual rings to be temporarily ... | 06/27/2006 |
| 7069391 | Method for improved first level cache coherency A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalid... | 06/27/2006 |
| 7069384 | System and method for cache external writing and write shadowing A system (10) uses shared resources (44, 54) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (42, 52, 48). A reload buffer (44, 54) is used i... | 06/27/2006 |
| 7062609 | Method and apparatus for selecting transfer types A transfer type selector selects a transfer type used for maintaining cache coherency according to address values used for accessing memory and is programmable so that different transfer types can be selected for different applications. In one embodiment, a table ha... | 06/13/2006 |
| 7062610 | Method and apparatus for reducing overhead in a data processing system with a cache A data processor (120) recognizes a special data processing operation in which data will be stored in a cache (124) for one use only. The data processor (120) allocates a memory location to at least one cache line of the cache (124). A da... | 06/13/2006 |
| 7062612 | Updating remote locked cache A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the... | 06/13/2006 |
| 7062613 | Methods and apparatus for cache intervention Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds ... | 06/13/2006 |
| 7058078 | Communication apparatus and a method of operating a communication apparatus A communication apparatus is provided that includes a first coding unit for creating first coded data including an audio signal coded by a first audio coding method, a second coding unit for creating second coded data including an audio signal coded by a second audi... | 06/06/2006 |
| 7055005 | Methods and apparatus used to retrieve data from memory into a RAM controller before such data is requested A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The RAM controller may store such data into a prefetch buffer. ... | 05/30/2006 |
| 7054997 | Disk array system and cache control method Disclosed is a disk array system that can be expanded effectively in scale by increasing the number of input/output channels and disk adapters and improved in such performance as the number of input/output operations per second, data transfer rate. The disk array sy... | 05/30/2006 |
| 7051102 | Peer-to-peer name resolution protocol (PNRP) security infrastructure and method A security infrastructure and methods are presented that inhibit the ability of a malicious node from disrupting the normal operations of a peer-to-peer network. The methods of the invention allow both secure and insecure identities to be used by nodes by making the... | 05/23/2006 |
| 7051177 | Method for measuring memory latency in a hierarchical memory system A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The ... | 05/23/2006 |
| 7050061 | Autonomous address translation in graphic subsystem A texture caching controller, located on the graphics card, handles address logical-to-physical translation for texture addresses which are not downloaded to level-1 memory due to low use or dynamically changing values. This offloads texture memory management duties... | 05/23/2006 |
| 7047351 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 05/16/2006 |
| 7047341 | Multi-processing memory duplication system Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor r... | 05/16/2006 |
| 7047366 | QOS feature knobs Described are various quality of service (QOS) parameters that may be used in characterizing device behavior in connection with a cache. A Partition parameter indicates which portions of available cache may used with data of an associated device. A Survival paramete... | 05/16/2006 |
| 7043612 | Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain ... | 05/09/2006 |
| 7039747 | Selective smart discards with prefetchable and controlled-prefetchable address space A bridging device has a first port to allow the device to communicate with other devices on an expansion bus and a second port to allow the device to communicate with devices on a second bus. The device also includes a memory to store data and a processor or logic t... | 05/02/2006 |
| 7039768 | Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of th... | 05/02/2006 |
| 7035986 | System and method for simultaneous access of the same line in cache storage An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same line detection unit receives a plurality of... | 04/25/2006 |
| 7035981 | Asynchronous input/output cache having reduced latency The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device in... | 04/25/2006 |
| 7035908 | Method for multiprocessor communication within a shared memory architecture An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pas... | 04/25/2006 |
| 7035958 | Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in... | 04/25/2006 |
| 7032079 | System and method for accelerating read requests within a multiprocessor system A system and method for managing memory data within a data processing system is disclosed. A main memory is provided to store data signals. When the main memory receives a request to read data signals, the main memory determines whether an updated copy of the reques... | 04/18/2006 |
| 7032078 | Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency. A node is form... | 04/18/2006 |
| 7028166 | System and method for linking speculative results of load operations to register values A system may include a memory file, which includes an entry configured to store a first addressing pattern and a first tag, and an execution core coupled to the memory file. The memory file may be configured to compare the first addressing pattern included in the en... | 04/11/2006 |
| 7028146 | Method of verifying a system in which a plurality of master devices share a storage region In logical verification of a system in which a plurality of master devices share a storage region, a scoreboard common to all master devices is provided. When starting verification, an initial value of data stored in each address of each storage device is set in cor... | 04/11/2006 |
| 7028292 | Program executing apparatus, control method therefor, and storage medium for interpreting and executing intermediate codes In a program executing apparatus, a code reading section reads intermediate codes into a storage unit. A data-reference analyzing section determines whether the operands of instructions in the intermediate codes stored in the storage unit require a data reference. E... | 04/11/2006 |
| 7024521 | Managing sparse directory evictions in multiprocessor systems via memory locking Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 04/04/2006 |
| 7020148 | Data transferring apparatus and data transferring method that use fast ring connection A data transferring apparatus includes a ring bus, which circularly transfers data by holding in a slot to one direction and a plurality of nodes connected to the ring bus. Each of the plurality of nodes includes a detector and a controller. The detector detects whe... | 03/28/2006 |
| 7020752 | Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of s... | 03/28/2006 |
| 7017054 | Mirrored tag snoop optimization A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory co... | 03/21/2006 |
| 7015921 | Method and apparatus for memory access An apparatus, in a data processing system having at least one host processor with host processor cache and host memory, includes a chip interconnect, a cache coherent interface coupled to the chip interconnect wherein the cache coherent interface provides cache cohe... | 03/21/2006 |
