Bizarre Patents
Hands free towel carrying system
A hands free towel carrying system for coupling a towel to a user to prevent loss, theft or contamination.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5455925 | Data processing device for maintaining coherency of data stored in main memory, external cache memory and internal cache memory A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory... | 10/03/1995 |
| 5446863 | Cache snoop latency prevention apparatus A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the... | 08/29/1995 |
| 5428761 | System for achieving atomic non-sequential multi-word operations in shared memory A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a write-back cache). The CPU performs some operation to alter or use the data item while it is in... | 06/27/1995 |
| 5426765 | Multiprocessor cache abitration A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access o... | 06/20/1995 |
| 5404489 | System and method for minimizing cache interruptions by inhibiting snoop cycles if access is to an exclusive page A memory property tagging apparatus is interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network ... | 04/04/1995 |
| 5398325 | Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a ... | 03/14/1995 |
| 5379402 | Data processing device for preventing inconsistency of data stored in main memory and cache memory A comparing unit compares an address of data written into a main memory by an external device with an address of data stored in a cache memory, and a masking unit masks specific bits obtained by a result in said address comparing unit. An invalidating uni... | 01/03/1995 |
| 5361340 | Apparatus for maintaining consistency in a multiprocessor computer system using virtual caching A computer system includes first and second processors each having a virtual cache memory, a main memory, a bus coupled to the main memory and the processors, and apparatus for addressing the cache associated with each processor for providing that the dat... | 11/01/1994 |
| 5355467 | Second level cache controller unit and system A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem i... | 10/11/1994 |
| 5345578 | Competitive snoopy caching for large-scale multiprocessors A system and method of satisfying read and write requests is used in a system having a plurality of cache-equipped processors coupled into a hypercube structure via buses, where each processor is simultaneously coupled to other processors on other buses v... | 09/06/1994 |
| 5341487 | Personal computer having memory system with write-through cache and pipelined snoop cycles A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before... | 08/23/1994 |
| 5339399 | Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is ex... | 08/16/1994 |
| 5335335 | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latc... | 08/02/1994 |
| 5325503 | Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the... | 06/28/1994 |
| 5319768 | Control circuit for resetting a snoop valid bit in a dual port cache tag memory A control circuit for a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the dual ports. This port snoops a main memory bus, and a cache tag hit which occurs during a write operation to the main memory bu... | 06/07/1994 |
| 5319766 | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a ... | 06/07/1994 |
| 5276849 | Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of less than a word in length, the write data stored within a FIFO memory device 18 associated wit... | 01/04/1994 |
| 5265235 | Consistency protocols for shared memory multiprocessors A shared memory multiprocessor having a packet switched bus, together with write back caches for connecting individual processor to that bus, employs a consistency protocol that permits the caches to store multiple copies of read/write data at identical p... | 11/23/1993 |
| 5261106 | Semaphore bypass The present invention provides a test and set bypass mechanism which allows access to a semaphore while eliminating memory bandwidth degradation due to the traditional "spin-locking" problem. Generally, a storage and comparison structure in a processor, s... | 11/09/1993 |
| 5249283 | Cache coherency method and apparatus for a multiple path interconnection network A method and apparatus for providing coherency for cache data in a multiple processor system with the processors distributed among multiple independent data paths. The apparatus includes a set of cache monitors, sometimes called snoopers, associated with ... | 09/28/1993 |
| 5228135 | Multiport cache memory control unit including a tag memory having plural address ports and a snoop address part A multiport cache memory control unit includes a central processing unit having N arithmetic units for executing arithmetic processing, a tag memory having N address ports for storing addresses, a multiport cache memory having N data ports for storing pie... | 07/13/1993 |
| 5228134 | Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across t... | 07/13/1993 |
| 5193170 | Methods and apparatus for maintaining cache integrity whenever a CPU write to ROM operation is performed with ROM mapped to RAM Methods and apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM ... | 03/09/1993 |
| 5185878 | Programmable cache memory as well as system incorporating same and method of operating programmable cache memory Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing appl... | 02/09/1993 |
| 5133074 | Deadlock resolution with cache snooping A device for resolving deadlock between a local processor and system resources for access to a local store in a multiprocessor data processing system having high speed cache comprises an address storage device, deadlock resolution logic and a deadlock det... | 07/21/1992 |
| 5119485 | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache ... | 06/02/1992 |
| 5072369 | Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on... | 12/10/1991 |
| 4959777 | Write-shared cache circuit for multiprocessor system A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order ... | 09/25/1990 |
| 4939641 | Multi-processor system with cache memories A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memor... | 07/03/1990 |
| 4858111 | Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache A computer system in which only the cache memory is permitted to communicate with main memory and the same address being used in the cache is also sent at the same time to the main memory. Thus, as soon as it is discovered that the desired main memory add... | 08/15/1989 |
| 4785398 | Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis fo... | 11/15/1988 |
| 4141067 | Multiprocessor system with cache memory A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to rea... | 02/20/1979 |
