Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7730266 | Adaptive range snoop filtering methods and apparatuses Snoop filtering methods and apparatuses for systems utilizing memory are contemplated. Method embodiments comprise receiving a request for contents of a memory line by a home agent, comparing an address of the memory line to a range in a set of adaptive ranges, and ... | 06/01/2010 |
| 7698509 | Snooping-based cache-coherence filter for a point-to-point connected multiprocessing node A multiprocessing node has a plurality of point-to-point connected microprocessors. Each of the microprocessors is also point-to-point connected to a filter. In response to a local cache miss, a microprocessor issues a broadcast for the requested data to the filter.... | 04/13/2010 |
| 7694081 | Storage system and method for controlling storage system The invention aims at improving the scalability of a storage system using a switch with a small number of ports. A storage system includes a plurality of host connection control units 10 connected to host computers; a plurality of drive control units | 04/06/2010 |
| 7694080 | Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in... | 04/06/2010 |
| 7689778 | Preventing system snoop and cross-snoop conflicts In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts wi... | 03/30/2010 |
| 7673104 | Information processing apparatus, system controller, local snoop control method, and local snoop control program recorded computer-readable recording medium The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality of storage units. For shortening the processing time needed for a mem... | 03/02/2010 |
| 7669013 | Directory for multi-node coherent bus A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a sys... | 02/23/2010 |
| 7669012 | Insertion of coherence requests for debugging a multiprocessor A method and system are disclosed to insert coherence events in a multiprocessor computer system, and to present those coherence events to the processors of the multiprocessor computer system for analysis and debugging purposes. The coherence events are inserted in ... | 02/23/2010 |
| 7669011 | Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, a... | 02/23/2010 |
| 7653790 | Methods and apparatus for responding to a request cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluste... | 01/26/2010 |
| 7644237 | Method and apparatus for global ordering to insure latency independent coherence A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to appl... | 01/05/2010 |
| 7636815 | System and method for handling direct memory accesses Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known ... | 12/22/2009 |
| 7617366 | Method and apparatus for filtering snoop requests using mulitiple snoop caches A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associati... | 11/10/2009 |
| 7613885 | Cache coherency control method, chipset, and multi-processor system In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy ta... | 11/03/2009 |
| 7603523 | Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises provid... | 10/13/2009 |
| 7603524 | Method and apparatus for filtering snoop requests using multiple snoop caches A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port... | 10/13/2009 |
| 7590805 | Monitor implementation in a multicore processor with inclusive LLC A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snoopin... | 09/15/2009 |
| 7584330 | Multi-processor data coherency A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable outside the processor. The method includes requesting data associated... | 09/01/2009 |
| 7584331 | Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associat... | 09/01/2009 |
| 7581068 | Exclusive ownership snoop filter A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a processor. A coherency engine updates the entries in the snoop filter such t... | 08/25/2009 |
| 7577797 | Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain incl... | 08/18/2009 |
| 7523268 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is disp... | 04/21/2009 |
| 7512743 | Using shared memory with an execute-in-place processor and a co-processor The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host proc... | 03/31/2009 |
| 7502895 | Techniques for reducing castouts in a snoop filter Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate... | 03/10/2009 |
| 7484046 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 01/27/2009 |
| 7472232 | Method and related apparatus for internal data accessing of computer system Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single vi... | 12/30/2008 |
| 7451277 | Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is se... | 11/11/2008 |
| 7447844 | Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a f... | 11/04/2008 |
| 7447845 | Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a r... | 11/04/2008 |
| 7437520 | Adaptive snoop-and-forward mechanisms for multiprocessor systems In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be... | 10/14/2008 |
| 7434008 | System and method for coherency filtering Systems and methods for coherency filtering are disclosed. A system may comprise a coherency filter that provides information identifying a coherency domain for data in an associated address space based on an identifier for the data. A snoop engine is configured to ... | 10/07/2008 |
| 7418558 | Information processing system, system control apparatus, and system control method A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received extern... | 08/26/2008 |
| 7418559 | Address snoop method and multi-processor system Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the upper limit of the performance of the multi-processor system from det... | 08/26/2008 |
| 7418557 | Managing multiprocessor operations In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the share... | 08/26/2008 |
| 7418556 | Accessing memory and processor caches of nodes in multi-node configurations A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other no... | 08/26/2008 |
| 7409481 | Data processing system, method and interconnect fabric supporting destination data tagging A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plu... | 08/05/2008 |
| 7409500 | Systems and methods for employing speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requ... | 08/05/2008 |
| 7409504 | Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes seve... | 08/05/2008 |
| 7409503 | Register file systems and methods for employing speculative fills Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are ... | 08/05/2008 |
| 7406571 | Memory system and method for controlling the same, and method for maintaining data coherency A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporar... | 07/29/2008 |
