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| Number | Title | Issue Date |
| 6950909 | System and method for reducing contention in a multi-sectored cache A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache directory updates. When a first queue issues a write access request for a f... | 09/27/2005 |
| 6948009 | Method, system, and article of manufacture for increasing processor utilization Provided are a method, system, and program for increasing processor utilization. A list of work is divided for processing among a plurality of processes, wherein a process is allocated a part of the list of work to process, and the processes execute in parallel. If ... | 09/20/2005 |
| 6947971 | Ethernet packet header cache Methods and apparatus for caching information associated with packets are disclosed. According to one aspect of the present invention, a system for processing a packet includes a controller with a processor and a controller data cache, a bus, a memory interface, and... | 09/20/2005 |
| 6944721 | Asynchronous non-blocking snoop invalidation A method and system for avoiding live locks caused by repeated retry responses sent from a first cache memory that is in the process of manipulating a cache line that a second cache memory is attempting invalidate in the first cache memory. To a live lock condition ... | 09/13/2005 |
| 6944743 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/13/2005 |
| 6944698 | Method and apparatus for providing bus arbitrations in a data processing system A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a... | 09/13/2005 |
| 6937057 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 08/30/2005 |
| 6934813 | System and method for caching data based on identity of requestor In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination ... | 08/23/2005 |
| 6934770 | Method for aborting data transfer commands A single hardware I/O control block is used to efficiently abort a target I/O command for a target I/O device, e.g., one target I/O device in a plurality of target I/O devices. The abort command is included in the same hardware I/O control block that specified the t... | 08/23/2005 |
| 6934720 | Automatic invalidation of cached data A system and method are provided for automatically invalidating cached data. A cache system caches data from a data server (e.g., web server, application server, database). When a request is received at the cache system from a client, particularly a request to alter... | 08/23/2005 |
| 6934807 | Determining an amount of data read from a storage medium Data is read in response to a request for a predetermined amount of data. The amount of data that has been read is determined prior to completing reading the predetermined amount of data. The predetermined amount of data may include prefetch data and demand data, wh... | 08/23/2005 |
| 6931495 | Processor and method of arithmetic processing thereof A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back informati... | 08/16/2005 |
| 6931505 | Distributed memory module cache command formatting One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 08/16/2005 |
| 6931510 | Method and system for translation lookaside buffer coherence in multiprocessor systems This invention is an apparatus, method, and system for translational lookaside buffer coherency in computer systems having a plurality of processors, each having an associated TLB for storing address translation data, and the computer system having a plurality of in... | 08/16/2005 |
| 6928517 | Method for avoiding delays during snoop requests A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate a... | 08/09/2005 |
| 6928525 | Per cache line semaphore for cache access arbitration A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whet... | 08/09/2005 |
| 6928520 | Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory... | 08/09/2005 |
| 6927614 | High performance state saving circuit A state saving circuit includes a state saving latch powered by an un-interruptible power supply, and a cut-off control device powered by the un-interruptible power supply that selectively connects the state saving latch to a pair of latch nodes based upon a control... | 08/09/2005 |
| 6925536 | Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 08/02/2005 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol... | 08/02/2005 |
| 6922756 | Forward state for use in cache coherency in a multiprocessor system Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. ... | 07/26/2005 |
| 6922755 | Directory tree multinode computer system A multinode, multiprocessor computer system with distributed shared memory has reduced hardware and improved performance by providing a directory free environment. Without a directory, nodes do not track where cache lines are stored in caches on other nodes. In two-... | 07/26/2005 |
| 6920532 | Cache coherence directory eviction mechanisms for modified copies of memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 07/19/2005 |
| 6918012 | Streamlined cache coherency protocol system and method for a multiple processor single chip device A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending state... | 07/12/2005 |
| 6912648 | Stick and spoke replay with selectable delays A method for stick and spoke replay in a processor. The method of one embodiment comprises dispatching an instruction for execution. The instruction is speculatively executed. It is determined whether the instruction executed correctly. The instruction is routed to ... | 06/28/2005 |
| 6910062 | Method and apparatus for transmitting packets within a symmetric multiprocessor system The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter numb... | 06/21/2005 |
| 6907502 | Method for moving snoop pushes to the front of a request queue A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the o... | 06/14/2005 |
| 6907512 | System and method for filtering write operations to a storage medium containing an operating system image A write filter is used to handle write operations by an operating system of a computing device that has a main storage medium in which the operating system image is stored. The write filter is placed in the operating system to intercept write commands for writing st... | 06/14/2005 |
| 6898675 | Data received before coherency window for a snoopy bus Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be determined, for example, from the availability of the data without a bus tra... | 05/24/2005 |
| 6898676 | Computer system supporting both dirty-shared and non-dirty-shared data processing entities A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of... | 05/24/2005 |
| 6895477 | Ring-based memory requests in a shared memory multi-processor A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first processing cluster forwards a memory request to the snoop controller... | 05/17/2005 |
| 6892282 | Ring based multi-processing system A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory requests from each processing cluster. The data ring enables cluster... | 05/10/2005 |
| 6883070 | Bandwidth-adaptive, hybrid, cache-coherence protocol A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the i... | 04/19/2005 |
| 6880031 | Snoop phase in a highly pipelined bus architecture A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this emb... | 04/12/2005 |
| 6877029 | Method and apparatus for managing node controllers using partitions in a computer system A partitioned computer system (32) includes a plurality of node controllers (12) connected by a network (14) and partitioned into a plurality of partitioned groups (40). A requesting node controller (34) in one partitioned group ( | 04/05/2005 |
| 6871267 | Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the cache line to a transition cache. Based on the system response to the ... | 03/22/2005 |
| 6871268 | Methods and systems for distributed caching in presence of updates and in accordance with holding times Techniques for improved cache management including cache replacement are provided. In one aspect, a distributed caching technique of the invention comprises the use of a central cache and one or more local caches. The central cache communicates with the one or more ... | 03/22/2005 |
| 6865649 | Method and apparatus for pre-fetching data during program execution A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or all of the basic blocks (e.g., a table is associated with, or stores... | 03/08/2005 |
| 6865595 | Methods and apparatus for speculative probing of a remote cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or ... | 03/08/2005 |
| 6862665 | Method, system, and apparatus for space efficient cache coherency A schematic, system, and flowchart to facilitate storage of directory information for a cache coherency protocol. The protocol allows for at least a single bit of directory information overwriting data stored in a cache coherency unit based at least in part on at le... | 03/01/2005 |
