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| Number | Title | Issue Date |
| 8117401 | Interconnect operation indicating acceptability of partial data delivery According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable am... | 02/14/2012 |
| 8103836 | Snoop filtering system in a multiprocessor system A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, ea... | 01/24/2012 |
| 8099560 | Synchronization mechanism for use with a snoop queue In a data processing system each bus master of a plurality of bus masters communicates information via a system interconnect. A cache is associated with a predetermined bus master of the plurality of bus masters for storing information used by the predetermined bus ... | 01/17/2012 |
| 8037253 | Method and apparatus for global ordering to insure latency independent coherence A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to appl... | 10/11/2011 |
| 8032717 | Memory control apparatus and method using retention tags A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for... | 10/04/2011 |
| 8028131 | System and method for aggregating core-cache clusters in order to produce multi-core processors According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor ... | 09/27/2011 |
| 8024527 | Partial cache line accesses based on memory access patterns According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multi... | 09/20/2011 |
| 8015366 | Accessing memory and processor caches of nodes in multi-node configurations A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other no... | 09/06/2011 |
| 8015365 | Reducing back invalidation transactions from a snoop filter In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with th... | 09/06/2011 |
| 8015364 | Method and apparatus for filtering snoop requests using a scoreboard An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structure... | 09/06/2011 |
| 7996626 | Snoop filter optimization A snoop filter optimization system includes one or more subsystems to operate a snoop filter, determine information that that affects operation of the snoop filter, and adjust operation of the snoop filter relative to the information that affects operation of the sn... | 08/09/2011 |
| 7996625 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 08/09/2011 |
| 7987322 | Snoop request management in a data processing system Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue ... | 07/26/2011 |
| 7979644 | System controller and cache control method A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communi... | 07/12/2011 |
| 7941611 | Filtering snooped operations A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the ca... | 05/10/2011 |
| 7937535 | Managing cache coherency in a data processing apparatus Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filteri... | 05/03/2011 |
| 7937536 | Handling direct memory accesses Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known ... | 05/03/2011 |
| 7925840 | Data processing apparatus and method for managing snoop operations The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least ... | 04/12/2011 |
| 7904665 | Multiprocessor system and its operational method The multiprocessor system includes multiple cells having identical functions, and each of the multiple cells has a processor, a cache memory, and a main memory. The multiple cells include the first cell as a request cell, the second cell as a home cell, and the thir... | 03/08/2011 |
| 7877551 | Programmable partitioning for high-performance coherence domains in a multiprocessor system A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units incl... | 01/25/2011 |
| 7856535 | Adaptive snoop-and-forward mechanisms for multiprocessor systems In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be... | 12/21/2010 |
| 7818511 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 10/19/2010 |
| 7805576 | Information processing system, information processing board, and method of updating cache tag and snoop tag In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system contro... | 09/28/2010 |
| 7783842 | Cache coherent I/O communication A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory... | 08/24/2010 |
| 7783843 | Bus interface adapted to coalesce snoop responses In a bus interface adapted for usage in a multiple-core processor, an interface couples a bus to the one or more processor cores. The bus interface comprises a queue coupled to the interface which is adapted to receive snoop responses from the processor cores and co... | 08/24/2010 |
| 7779209 | System controller, snoop tag modification method and information processing apparatus having snoop tag modification function In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the ad... | 08/17/2010 |
| 7779210 | Avoiding snoop response dependency In one embodiment, the present invention includes a method for receiving a request for data in a home agent of a system from a first agent, prefetching the data from a memory and accessing a directory entry to determine whether a copy of the data is cached in any sy... | 08/17/2010 |
| 7779211 | Reducing latency in responding to a snoop request In one embodiment, the present invention includes a method for receiving a snoop request, providing the snoop request to a coherency engine along a first path and providing the snoop request to a bypass logic along a bypass path, and generating a speculative invalid... | 08/17/2010 |
| 7774556 | Asymmetric memory migration in hybrid main memory Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the mai... | 08/10/2010 |
| 7765363 | Mask usable for snoop requests A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a... | 07/27/2010 |
| 7743218 | Updating an invalid coherency state in response to snooping an operation A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is se... | 06/22/2010 |
| 7734876 | Protecting ownership transfer with non-uniform protection windows In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure ... | 06/08/2010 |
| 7730266 | Adaptive range snoop filtering methods and apparatuses Snoop filtering methods and apparatuses for systems utilizing memory are contemplated. Method embodiments comprise receiving a request for contents of a memory line by a home agent, comparing an address of the memory line to a range in a set of adaptive ranges, and ... | 06/01/2010 |
| 7698509 | Snooping-based cache-coherence filter for a point-to-point connected multiprocessing node A multiprocessing node has a plurality of point-to-point connected microprocessors. Each of the microprocessors is also point-to-point connected to a filter. In response to a local cache miss, a microprocessor issues a broadcast for the requested data to the filter.... | 04/13/2010 |
| 7694080 | Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in... | 04/06/2010 |
| 7694081 | Storage system and method for controlling storage system The invention aims at improving the scalability of a storage system using a switch with a small number of ports. A storage system includes a plurality of host connection control units 10 connected to host computers; a plurality of drive control units | 04/06/2010 |
| 7689778 | Preventing system snoop and cross-snoop conflicts In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts wi... | 03/30/2010 |
| 7673104 | Information processing apparatus, system controller, local snoop control method, and local snoop control program recorded computer-readable recording medium The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality of storage units. For shortening the processing time needed for a mem... | 03/02/2010 |
| 7669013 | Directory for multi-node coherent bus A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a sys... | 02/23/2010 |
| 7669011 | Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, a... | 02/23/2010 |
