Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 6954828 | Management of caches in a data processing apparatus The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing a... | 10/11/2005 |
| 6952707 | Efficient sequence number generation in a multi-system data-sharing environment A method, apparatus, article of manufacture, and data structure for use in efficiently generating sequence numbers in a multi-system data-sharing environment. Sequence number assignment logic, performed by a computer system, generates a recoverable, unique sequence ... | 10/04/2005 |
| 6950907 | Enhanced protection for memory modification tracking with redundant dirty indicators A dirty memory subsystem includes storage operable to store redundant copies of dirty indicators. Each dirty indicator is associated with a respective block of main memory and is settable to a predetermined state to indicate that the block of main memory associated ... | 09/27/2005 |
| 6948011 | Alternate Register Mapping A novel method of providing alternate access to a storage element for holding a data element in a network interface. The storage element is accessed via a first access path when the network interface operates with a first type of software, and via a second access pa... | 09/20/2005 |
| 6944637 | Reduced size objects headers A method and apparatus for reducing memory requirements in a computing environment. The method includes reducing the size of a header for a data structure by creating a header consisting of index information. Alternatively, the header may also include garbage collec... | 09/13/2005 |
| 6944719 | Scalable cache coherent distributed shared memory processing system A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in distributed shared memory systems. The I/O link protocol is adapted to include additional virtual channels tha... | 09/13/2005 |
| 6944740 | Method for performing compressed I/O with memory expansion technology A method is provided for manipulating a compressed translation table in a memory expansion technology system. The method comprises swapping contents of an output buffer with contents of a compression buffer, disabling compression for compression translation table en... | 09/13/2005 |
| 6938129 | Distributed memory module cache One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 08/30/2005 |
| 6938128 | System and method for reducing memory latency during read requests A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the ... | 08/30/2005 |
| 6938130 | Method and apparatus for delaying interfering accesses from other threads during transactional program execution One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another t... | 08/30/2005 |
| 6934825 | Bi-directional stack in a linear memory array A method, system, and apparatus for placing and removing data elements into a bi-directionally growing first in last out data structure is provided. In one embodiment, in response to a request to place a data element into the data structure, a head pointer is advanc... | 08/23/2005 |
| 6934947 | Visual tool for developing real time task management code A tool for developing software code for real time system allows the user to structure scheduling of multi-tasking operations into a polling loop without the complexity of a hand-crafted polling loop, while preventing deadlocks between the real time tasks. The tool p... | 08/23/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6934806 | Method and system for improving input/output performance by proactively flushing and locking an entire page out of caches of a multiprocessor system A method (and system) of improving performance of a multiprocessor system, includes proactively flushing and locking an arbitrarily-sized region of memory out of caches of the multiprocessor system. ... | 08/23/2005 |
| 6931489 | Apparatus and methods for sharing cache among processors A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array... | 08/16/2005 |
| 6931495 | Processor and method of arithmetic processing thereof A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back informati... | 08/16/2005 |
| 6931629 | Method and apparatus for generation of validation tests A computer system and a computer-implemented method for generating test programs that satisfy at least one termination criterion. The computer system includes a hardware unit to transmit data. A processor is coupled to the hardware unit and to a storage device. The ... | 08/16/2005 |
| 6928525 | Per cache line semaphore for cache access arbitration A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whet... | 08/09/2005 |
| 6928522 | Unbalanced inclusive tags The disclosed embodiments may relate to cache memory systems. A multiprocessor computer system may include multiple processors and caches that may be organized in a hierarchical configuration. The caches may be organized into lines and include data and cache tags. D... | 08/09/2005 |
| 6928521 | Method, system, and data structures for using metadata in updating data in a storage device Disclosed is a method, system, and data structures for updating data in a storage device. An update to one or more blocks of customer data at addresses in the storage device is received. For each block of data to update, metadata is generated indicating the address ... | 08/09/2005 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol... | 08/02/2005 |
| 6925546 | Memory pool configuration system A memory partitioning system for memory of an embedded or auxiliary processor is described. Memory regions with different attributes are formed, having specified cacheability and visibility characteristics. A configurable table describes the memory regions required ... | 08/02/2005 |
| 6925536 | Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 08/02/2005 |
| 6922745 | Method and apparatus for handling locks A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences asso... | 07/26/2005 |
| 6922756 | Forward state for use in cache coherency in a multiprocessor system Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. ... | 07/26/2005 |
| 6920543 | Method and apparatus for performing distributed processing of program code A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queui... | 07/19/2005 |
| 6920532 | Cache coherence directory eviction mechanisms for modified copies of memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 07/19/2005 |
| 6920533 | System boot time reduction method A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the ... | 07/19/2005 |
| 6918012 | Streamlined cache coherency protocol system and method for a multiple processor single chip device A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending state... | 07/12/2005 |
| 6918013 | System and method for flushing bean cache Servers in a network cluster can each store a copy of a data item in local cache, providing read access to these copies through read-only entity beans. The original data item in the database can be updated through a read/write entity bean one of the cluster servers.... | 07/12/2005 |
| 6918015 | Scalable directory based cache coherence protocol A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. ... | 07/12/2005 |
| 6915388 | Method and system for efficient use of a multi-dimensional sharing vector in a computer system A multiprocessor computer system includes a plurality of processor nodes, a memory, and an interconnect network connecting the plurality of processor nodes to the memory. The memory includes a plurality of lines and a cache coherence directory structure. The plurali... | 07/05/2005 |
| 6915387 | System and method for handling updates to memory in a distributed shared memory system A processor (100) in a distributed shared memory computer system (10) receives ownership of data and initiates an initial update to memory request. A front side bus processor interface (24) forwards the initial update to memory request to a memo... | 07/05/2005 |
| 6912669 | Method and apparatus for maintaining cache coherency in a storage system A method and apparatus for cache coherency in storage system is disclosed. The invention maintains cache coherency in the controller system of the storage system in a manner to minimize the performance degradation to a host system, and to allow the caches to be cohe... | 06/28/2005 |
| 6912628 | N-way set-associative external cache with standard DDR memory devices A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory d... | 06/28/2005 |
| 6912623 | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage ... | 06/28/2005 |
| 6912624 | Method and system for exclusive two-level caching in a chip-multiprocessor To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in ... | 06/28/2005 |
| 6910212 | System and method for improved complex storage locks An improved system and method for improving complex storage locks that manage access to a shared resource. A FIFO queue is maintained for processes waiting to read or write to the shared resource. When the shared resource is available, the first item is read from th... | 06/21/2005 |
| 6910104 | Icache-based value prediction mechanism An apparatus for executing an instruction in a computational pipeline includes a first instruction memory. The first instruction memory includes a first plurality of instruction fields, each of which is capable of holding an instruction therein. Each of a first plur... | 06/21/2005 |
| 6910107 | Method and apparatus for invalidation of data in computer systems Methods and systems consistent with this invention conserve computer resources in a hierarchical memory system by preventing scratch data from unnecessarily being copied from a lower hierarchy to a higher hierarchy storage space. Such methods and systems invalidate ... | 06/21/2005 |
