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| Number | Title | Issue Date |
| 5490261 | Interlock for controlling processor ownership of pipelined data for a store in cache Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ow... | 02/06/1996 |
| 5487162 | Cache lock information feeding system using an address translator A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache loc... | 01/23/1996 |
| 5481706 | System and method for creating thread-safe shared libraries Libraries for use in a multithreaded computer environment which must be thread-safe and cannot be recoded are identified. Such libraries, after identification, are repackaged. Export routines for such libraries will thereby acquire a front end which effec... | 01/02/1996 |
| 5479634 | Multiprocessor cache memory unit selectively enabling bus snooping during in-circuit emulation A cache memory unit for use in a multiprocessor. The unit includes a data memory, a tag memory, a valid flag section, and an address bus, a comparator, and a clear signal producing section which produces a monitoring clear signal based on an output from t... | 12/26/1995 |
| 5442763 | System and method for preventing deadlock in multiprocessor multiple resource instructions A system and method for preventing deadlock in a multiprocessor computer system executing instructions requiring multiple resources. The system detects potential deadlock situations where a multi-resource instruction is blocked from obtaining one of the r... | 08/15/1995 |
| 5428761 | System for achieving atomic non-sequential multi-word operations in shared memory A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a write-back cache). The CPU performs some operation to alter or use the data item while it is in... | 06/27/1995 |
| 5404482 | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding c... | 04/04/1995 |
| 5353428 | Information processing apparatus in which a cache memory can be operated in both store-in and store-through modes In an information processing apparatus composed of two or more processor units each including a cache memory and a processor which accesses stored data via the cache memory, and a main storage, a cache memory control method in which, using information con... | 10/04/1994 |
| 5353431 | Memory address decoder with storage for memory attribute information A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder ... | 10/04/1994 |
| 5319768 | Control circuit for resetting a snoop valid bit in a dual port cache tag memory A control circuit for a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the dual ports. This port snoops a main memory bus, and a cache tag hit which occurs during a write operation to the main memory bu... | 06/07/1994 |
| 5319766 | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a ... | 06/07/1994 |
| 5301290 | Method for minimizing lock processing while ensuring consistency among pages common to local processor caches and a shared external store A computer implemented method for minimizing the grant of pages locks and the number of outstanding locks while ensuring consistency of the copies of pages resident among a first, and a second data cache with the original pages in shared external storage.... | 04/05/1994 |
| 5297269 | Cache coherency protocol for multi processor computer system A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when ... | 03/22/1994 |
| 5261069 | Method of maintaining consistency of cached data in a database system A method of maintaining the consistency of cached data in a client-server database system. Three new locks--a cache lock, a pending lock and an out-of-date lock--are added to a two-lock concurrency control system. A new long-running envelope transaction h... | 11/09/1993 |
| 5230070 | Access authorization table for multi-processor caches A multi-processor (MP) system having shared storage is provided with locking of exclusivity status and read only status in multi-processor caches. The multi-processor system includes a plurality of processors, a shared main storage and a storage control e... | 07/20/1993 |
| 5226143 | Multiprocessor system includes operating system for notifying only those cache managers who are holders of shared locks on a designated page by global lock manager A conditional broadcast or notification facility of a global lock manager is utilized to both serialize access to pages stored in local caches of counterpart processors in a distributed system and to ensure consistency among pages common to the caches. Ex... | 07/06/1993 |
| 5197146 | Method for maintaining cache coherence in a multiprocessor computer system A method is provided for maintaining cache coherence in a multiprocessor computer system having a potential for duplication of data in a plurality of storage location, where there is cache associated with each processor by storing a processor address and ... | 03/23/1993 |
| 5197139 | Cache management for multi-processor systems utilizing bulk cross-invalidate A store through cache environment managed exclusively grants exclusivity on a large granularity basis. A cross-invalidate is realized for all changed lines via a single transmission when exclusivity is released. A dynamic table that operates in conjunctio... | 03/23/1993 |
| 5163143 | Enhanced locked bus cycle control in a cache memory computer system An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the c... | 11/10/1992 |
| 5146603 | Copy-back cache system having a plurality of context tags and setting all the context tags to a predetermined value for flushing operation thereof A data memory system includes a main memory and a copy-back cache. Each line of the cache has a context tag, which is compared with a current context number to test whether the line contains the required data. The cache can be flushed simply by resetting ... | 09/08/1992 |
| 5113514 | System bus for multiprocessor computer system The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the cond... | 05/12/1992 |
| 5097409 | Multi-processor system with cache memories A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storag... | 03/17/1992 |
| 5045996 | Multiprocessor cache memory housekeeping Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a lau... | 09/03/1991 |
| 5043886 | Load/store with write-intent for write-back caches A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also d... | 08/27/1991 |
| 5029072 | Lock warning mechanism for a cache In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed using translation tables in the memory. The PMMU maintains a set of rec... | 07/02/1991 |
| 5025366 | Organization of an integrated cache unit for flexible usage in cache system design Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance w... | 06/18/1991 |
| 4977498 | Data processing system having a data memory interlock coherency scheme This invention is directed to a memory system that determines which blocks of a set of associative blocks in cache memory are unavailable for replacement. This is accomplished by operating the memory system to maintain a duplicate set of tags which track ... | 12/11/1990 |
| 4959777 | Write-shared cache circuit for multiprocessor system A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order ... | 09/25/1990 |
| 4939641 | Multi-processor system with cache memories A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memor... | 07/03/1990 |
| 4928225 | Coherent cache structures and methods A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand ca... | 05/22/1990 |
| 4924379 | Multiprocessor system with several processors equipped with cache memories and with a common memory In such a multiprocessor, in which the common memory (M) or one of the cache memories (C1, C2) can be owner of a variable determined by its address and in which it is always only the owner of a variable which delivers it to the bus (1) following a read re... | 05/08/1990 |
| 4775955 | Cache coherence mechanism based on locking A method and apparatus is provided for associating in cache directories the Control Domain Identifications (CDIDs) of software covered by each cache line. Through the use of such provision and/or the addition of Identifications of users actively using lin... | 10/04/1988 |
| 4755930 | Hierarchical cache memory system and method A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher ... | 07/05/1988 |
| 4513367 | Cache locking controls in a multiprocessor A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the... | 04/23/1985 |
| 4484267 | Cache sharing control in a multiprocessor The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC... | 11/20/1984 |
| 4410946 | Cache extension to processor local storage The disclosure pertains to a relatively small local storage (LS) in a processor's IE which can be effectively expanded by utilizing a portion of a processor's store-in-cache. The cache allocates a line (i.e. block) for LS use by the instruction unit sendi... | 10/18/1983 |
| 4394731 | Cache storage line shareability control for a multiprocessor system A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line posit... | 07/19/1983 |
