Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7386679 | System, method and storage medium for memory management A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer i... | 06/10/2008 |
| 7386671 | Smart cache A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mappe... | 06/10/2008 |
| 7386676 | Data coherence system A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device when it is initialized. If the two generations numbers are the same, t... | 06/10/2008 |
| 7380058 | Storage control apparatus, storage system, control method of storage control apparatus, channel control unit and program A storage control apparatus comprising a plurality of channel control units each having an interface with an information processor; a disk control unit having an interface with a storage device for storing data; a cache memory for storing temporarily data to be inte... | 05/27/2008 |
| 7376798 | Memory management methods and systems that support cache consistency Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In res... | 05/20/2008 |
| 7376684 | Efficient parallel bitwise sweep during garbage collection A method, system, and program for efficient parallel bitwise sweeps of larger objects during garbage collection are provided. During a bitwise sweep, a helper thread scans a mark vector looking for a consecutive sequence of unmarked bits of a sufficient length follo... | 05/20/2008 |
| 7376800 | Speculative multiaddress atomicity A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the sha... | 05/20/2008 |
| 7373459 | Congestion control and avoidance method in a data processing system A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of the request inputted from the client terminal, a first Uniform Resource Identifier (URI) check step of, wh... | 05/13/2008 |
| 7373457 | Cache coherence protocol for a multiple bus multiprocessor system A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, s... | 05/13/2008 |
| 7373462 | Snoop filter for filtering snoop requests A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises provid... | 05/13/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7370155 | Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to ... | 05/06/2008 |
| 7363433 | Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ... | 04/22/2008 |
| 7363316 | Systems and methods for organizing and mapping data A system and method is provided for organizing and mapping data. In exemplary embodiments, a copy of at least one first data block created from a first computing device is generated. A copy of one or more second data blocks created from one or more second computing ... | 04/22/2008 |
| 7363435 | System and method for coherence prediction A coherence prediction mechanism includes a synchronization manager and a plurality of access predictors. The synchronization manager maintains one or more sequence entries, each sequence entry indicating a sequence in which a corresponding data block is accessed by... | 04/22/2008 |
| 7363432 | Method and apparatus for directory-based coherence with distributed directory management A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data... | 04/22/2008 |
| 7363431 | Message-based distributed synchronization in a storage system Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint wi... | 04/22/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7360031 | Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O ag... | 04/15/2008 |
| 7360032 | Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache ... | 04/15/2008 |
| 7360033 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can ... | 04/15/2008 |
| 7359919 | Reliable request-response messaging over a request-response transport A reliable request-response mechanism allows a requesting computer system and a responding computer system in an established end-to-end connection to send and receive messages in a manner that the responding computer system processes a request as intended by the req... | 04/15/2008 |
| 7360069 | Systems and methods for executing across at least one memory barrier employing speculative fills Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills... | 04/15/2008 |
| 7356651 | Data-aware cache state machine A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the bottleneck to storage. The data-aware cache differentiates and manages dat... | 04/08/2008 |
| 7356647 | Cache with integrated capability to write out entire cache A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance p... | 04/08/2008 |
| 7350025 | System and method for improved collection of software application profile data for performance optimization The present invention is directed to a system and method for improved collection of application profile data for performance optimization. The invention provides a mechanism for storing usage bits within the hardware cache of a computing device. These usage bits pro... | 03/25/2008 |
| 7350033 | Methods and systems for providing validity logic Systems and methods are disclosed for providing validity logic. The disclosed systems and methods may include receiving at least one data value, determining validity data corresponding to the received at least one data value, and providing the validity data correspo... | 03/25/2008 |
| 7350034 | Architecture support of best-effort atomic transactions for multiprocessor systems An atomic transaction includes one or more memory access operations that are completed atomically. A Best-Effort Transaction (BET) system makes its best effort to complete each atomic transaction without guaranteeing completion of all atomic transactions. When an at... | 03/25/2008 |
| 7346737 | Cache system having branch target address cache A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the ... | 03/18/2008 |
| 7343395 | Facilitating resource access using prioritized multicast responses to a discovery request Systems and methods are provided to facilitate resource access using prioritized multicast responses to a discovery request. ... | 03/11/2008 |
| 7340565 | Source request arbitration Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may pr... | 03/04/2008 |
| 7340573 | Apparatus and method for controlling access to a memory unit The present invention provides a data processing apparatus and method for controlling access to a memory unit. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a sec... | 03/04/2008 |
| 7337278 | System, method and storage medium for prefetching via memory block tags A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag conte... | 02/26/2008 |
| 7337352 | Cache entry error-connecting code (ECC) based at least on cache entry data and memory address Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry in... | 02/26/2008 |
| 7334007 | Volume migration Systems and methods for performing an on-demand determination of a correct set of volumes to be exported are described. A disk platter is defined to be the unit of volume migration. Volumes are added to the platter based on whether or not the volume coexists on a di... | 02/19/2008 |
| 7334089 | Methods and apparatus for providing cache state information According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 02/19/2008 |
| 7330925 | Transaction flow control mechanism for a bus bridge A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC... | 02/12/2008 |
| 7328311 | Memory controller controlling cashed DRAM According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, b... | 02/05/2008 |
| 7328313 | Methods to perform cache coherency in multiprocessor system using reserve signals and control bits A cache controller prevents the use of data in a write-back cache memory from being propagated except to a client asserting a reserve signal, if a first control bit is set, or until the data is backed-up in a main memory, if a second control bit is set. The control ... | 02/05/2008 |
| 7324537 | Switching device with asymmetric port speeds In general, in one aspect, the disclosure describes a switching device that includes a plurality of ports. The ports operate at asymmetric speeds. The apparatus also includes a switching matrix to provide selective connectivity between the ports. The apparatus furth... | 01/29/2008 |
