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| Number | Title | Issue Date |
| 6789169 | Embedded DRAM cache memory and method having reduced latency A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system controller includes a system memory controller coupled to the system memory, a processor interface coupled... | 09/07/2004 |
| 6785776 | DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The... | 08/31/2004 |
| 6785774 | High performance symmetric multiprocessing systems via super-coherent data mechanisms A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency oper... | 08/31/2004 |
| 6785778 | Share masks and alias for directory coherency A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed leng... | 08/31/2004 |
| 6782453 | Storing data in memory In response to determining a requested line of data is not stored within a local memory, the requested line of data is written to the local memory from a remote memory. Additionally, a victim page is selected in the local memory in response to the requested line of ... | 08/24/2004 |
| 6782456 | Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions ... | 08/24/2004 |
| 6779086 | Symmetric multiprocessor systems with an independent super-coherent cache directory A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which ... | 08/17/2004 |
| 6779102 | Data processor capable of executing an instruction that makes a cache memory ineffective A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction fro... | 08/17/2004 |
| 6779088 | Virtual uncompressed cache size control in compressed memory systems A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enabl... | 08/17/2004 |
| 6775748 | Methods and apparatus for transferring cache block ownership Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the first cache holds the memory block in an “owned” state, and the ... | 08/10/2004 |
| 6772294 | Method and apparatus for using a non-committing data cache to facilitate speculative execution One embodiment of the present invention provides a system that facilitates speculative execution of instructions within a computer system. Upon encountering a stall during execution of an instruction stream, the system synchronizes a cache containing data that is be... | 08/03/2004 |
| 6772298 | Method and apparatus for invalidating a cache line without data return in a multi-node architecture A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidat... | 08/03/2004 |
| 6772299 | Method and apparatus for caching with variable size locking regions A method of managing data in a cache memory includes mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines, locking the first member of the plurality of cache lines creating a locked cache region and a... | 08/03/2004 |
| 6766419 | Optimization of cache evictions through software hints Program instructions permit software management of a processor cache. The program instructions may permit a software designer to provide software deallocation hints identifying data that is not likely to be used during further program execution. The program instruct... | 07/20/2004 |
| 6763433 | High performance cache intervention mechanism for symmetric multiprocessor systems Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache de... | 07/13/2004 |
| 6763434 | Data processing system and method for resolving a conflict between requests to modify a shared cache line Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modi... | 07/13/2004 |
| 6763435 | Super-coherent multiprocessor system bus protocols A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and resp... | 07/13/2004 |
| 6757793 | Reducing probe traffic in multiprocessor systems using a victim record table A victim record table records victim blocks which have been returned from a cache to memory and which are not currently cached in any other caches. If a command affecting a block recorded in the victim record table is received, one or more probes corresponding to th... | 06/29/2004 |
| 6757751 | High-speed, multiple-bank, stacked, and PCB-mounted memory module The density for any generation of Standard In-Line Memory Module (SIMM), or Dual In-Line-Memory Module (DIMM), chipset used to provide computer Random Access Memory (RAM), can be multiplied by surface-mounting multiple banks of SIMMs or DIMMs, where each bank occupi... | 06/29/2004 |
| 6757790 | Distributed, scalable data storage facility with cache memory The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory... | 06/29/2004 |
| 6757788 | CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU OR I/O DEVICE TO ACCESS TARGET BLOCK WITHOUT CACHE COHERENCE CONTROL, IF ASSOCIATED NODE HAS ACCESS RIGHT IN AN ACCESS RIGHT MEMORY TO TARGET BLOCK A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an exten... | 06/29/2004 |
| 6757789 | Apparatus and method for maximizing information transfers over limited interconnect resources The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data,... | 06/29/2004 |
| 6754784 | Methods and circuits for securing encached information A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable sec... | 06/22/2004 |
| 6751707 | Methods and apparatus for controlling a cache memory Methods and apparatus for controlling a cache memory are described in which the overwriting of floating point data into any cache line of the cache memory is prohibited when the data stored in such cache line are valid, integer data. ... | 06/15/2004 |
| 6748496 | Method and apparatus for providing cacheable data to a peripheral device A cache controller (210) includes a streaming memory attribute. The cache controller (210) is coupled to provide data from a cache line within a cache (228) to a memory (124) when both (a) the cache line is full and (b) the streaming memo... | 06/08/2004 |
| 6748518 | Multi-level multiprocessor speculation mechanism Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier i... | 06/08/2004 |
| 6748501 | Microprocessor reservation mechanism for a hashed address system A method of storing values in a sliced cache by providing separate, but coordinated, reservation units for each cache slice. When a load-with-reserve (larx) operation is issued from the processor core as part of an atomic read-modify-write sequence, a message is bro... | 06/08/2004 |
| 6745278 | Computer capable of rewriting an area of a non-volatile memory with a boot program during self mode operation of the computer There is provided a computer that can safely rewrite any one of the areas where a boot program is stored with fewer actions in the self-mode. A nonvolatile memory is divided into a plurality of areas, each of which is separately erasable and includes a user area and... | 06/01/2004 |
| 6745297 | Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an excl... | 06/01/2004 |
| 6745233 | Data transfer technique for distributed memory type parallel computer The object of the present invention is to speed up data transfer between processes required when there is a variable duplicatively assigned to a plurality of processes (duplicatively assigned variable) and any process among the plurality of processes substitutes dat... | 06/01/2004 |
| 6742104 | Master/slave processing system with shared translation lookaside buffer A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses μTLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon m... | 05/25/2004 |
| 6738865 | Method, system, and program for demoting data from cache based on least recently accessed and least frequently accessed data Disclosed is a method, system, and program for caching data. Data from a device, such as a volatile memory device or non-volatile storage device, is maintained in entries in a cache. For each entry in cache, a variable indicates both a time when the cache entry was ... | 05/18/2004 |
| 6738864 | Level 2 cache architecture for multiprocessor with task—ID and resource—ID A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 ... | 05/18/2004 |
| 6738869 | Arrangements for out-of-order queue cache coherency and memory write starvation prevention Arrangements for maintaining out-of-order queue cache coherency and for prevention of memory write starvation. ... | 05/18/2004 |
| 6735675 | Method and apparatus for altering data length to zero to maintain cache coherency Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent.... | 05/11/2004 |
| 6732239 | Concurrent access scheme for exclusive mode cache Methods for permitting concurrent access to an object in a data store of the type having an exclusive access cache are disclosed. The method uses first-in-last-out conditions to control which concurrent transaction, if there is more than one transaction pending for ... | 05/04/2004 |
| 6732234 | Direct access mode for a cache A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons a... | 05/04/2004 |
| 6728873 | System and method for providing multiprocessor speculation within a speculative branch path Disclosed is a method of operation within a processor, that enhances speculative branch processing. A speculative execution path contains an instruction sequence that includes a barrier instruction followed by a load instruction. While a barrier operation associated... | 04/27/2004 |
| 6725343 | System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cach... | 04/20/2004 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in ... | 04/20/2004 |
