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| Number | Title | Issue Date |
| 8171230 | PCI express address translation services invalidation synchronization with TCE invalidation A PCI Express (PCIe) computer system utilizes address translation services to translate virtual addresses from I/O device adaptors to physical addresses of system memory. A combined memory controller and host bridge uses a translation agent to convert the I/O addres... | 05/01/2012 |
| 8140773 | Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when... | 03/20/2012 |
| 8127085 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use ind... | 02/28/2012 |
| 8090914 | System and method for creating ordering points A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the s... | 01/03/2012 |
| 8082399 | Cache bounded reference counting Cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object ... | 12/20/2011 |
| 8051251 | Method and apparatus for setting status of cache memory One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory ... | 11/01/2011 |
| 8041900 | Method and apparatus for improving transactional memory commit latency Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a s... | 10/18/2011 |
| 8024526 | Multi-node system with global access states A system may include several nodes coupled by an inter-node network configured to convey coherency messages between the nodes. Each node may include several active devices coupled by an address network and a data network. The nodes implement a coherency protocol suc... | 09/20/2011 |
| 8015363 | Cache consistency in a multiprocessor system with shared memory A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the proc... | 09/06/2011 |
| 7991966 | Efficient usage of last level caches in a MCMP system using application level configuration This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon information configured by an application. An INC bit is set for each access to a page table that indicates whethe... | 08/02/2011 |
| 7966457 | Configurable cache for a microprocessor A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing in... | 06/21/2011 |
| 7962696 | System and method for updating owner predictors Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of ow... | 06/14/2011 |
| 7958319 | Hardware acceleration for a software transactional memory system A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardw... | 06/07/2011 |
| 7958320 | Protected cache architecture and secure programming paradigm to protect applications Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumve... | 06/07/2011 |
| 7904664 | Selectively monitoring loads to support transactional program execution One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor... | 03/08/2011 |
| 7873795 | Multi-process support in a shared register A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion a... | 01/18/2011 |
| 7865670 | Invalidating translation lookaside buffer entries in a virtual machine (VM) system One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the ... | 01/04/2011 |
| 7827151 | High availability via data services Application-level replication, the synchronization of data updates within a cluster of application servers, may be provided by having application servers themselves synchronize all updates to multiple redundant databases, precluding the need for database-level repli... | 11/02/2010 |
| 7818510 | Selectively monitoring stores to support transactional program execution One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processo... | 10/19/2010 |
| 7743217 | Cache consistency in a multiprocessor system with shared memory A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the proc... | 06/22/2010 |
| 7739456 | Method and apparatus for supporting very large transactions One embodiment of the present invention provides a system that executes a transaction on a multi-threaded processor. The system starts by executing the transaction in a “transaction-pending mode,” which involves placing load-marks or store-marks on cache lines l... | 06/15/2010 |
| 7725662 | Hardware acceleration for a software transactional memory system A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardw... | 05/25/2010 |
| 7689776 | Method and system for efficient cache locking mechanism Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is util... | 03/30/2010 |
| 7689777 | Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ... | 03/30/2010 |
| 7653789 | Multiprocessor system that supports both coherent and non-coherent memory accesses One embodiment of the present invention provides a system that reduces coherence traffic in a multiprocessor system by supporting both coherent memory accesses and non-coherent memory accesses. During operation, the system receives a request to perform a memory acce... | 01/26/2010 |
| 7606981 | System and method for reducing store latency According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast int... | 10/20/2009 |
| 7568073 | Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection A computer-implemented method for enforcing cache coherence includes multicasting a cache request for a memory address from a requesting node without an ordering restriction over a network, collecting, by the requesting node, a combined snoop response of the cache r... | 07/28/2009 |
| 7546422 | Method and apparatus for the synchronization of distributed caches A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching i... | 06/09/2009 |
| 7484045 | Store performance in strongly-ordered microprocessor architecture A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of ... | 01/27/2009 |
| 7437513 | Cache memory with the number of operated ways being changed according to access pattern An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a c... | 10/14/2008 |
| 7428615 | System and method for maintaining coherency and tracking validity in a cache hierarchy A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC... | 09/23/2008 |
| 7426627 | Selective address translation for a resource such as a hardware device A computing system has a resource for providing resource services, where each resource service is accessed by way of a system address (SA). A device requests the resource services of the resource by way of requests, where each request includes a remote address (RA) ... | 09/16/2008 |
| 7418555 | Multiprocessor system and method to maintain cache coherence A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the m... | 08/26/2008 |
| 7415556 | Exclusion control An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-p... | 08/19/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associat... | 06/17/2008 |
| 7389379 | Selective disk offlining A storage system with redundant mass storage device arrays determines that a mass storage device is non-responsive, and individually offlines the specific mass storage device for a temporary period. Reads to the offline mass storage device may be temporarily prevent... | 06/17/2008 |
| 7389383 | Selectively unmarking load-marked cache lines during transactional program execution One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering access... | 06/17/2008 |
| 7389388 | Data processing system and method for efficient communication utilizing an in coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memor... | 06/17/2008 |
| 7386676 | Data coherence system A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device when it is initialized. If the two generations numbers are the same, t... | 06/10/2008 |
