Bizarre Patents
Safety System For Remove a Rider From a Vehicle by Deploying a Parachute
Methods and apparatus for reducing the velocity of a rider in or on an open cockpit vehicle when the rider is thrown from the vehicle.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7127562 | Ensuring orderly forward progress in granting snoop castout requests A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus... | 10/24/2006 |
| 7124257 | Bus interface controller for determining access counts The present invention provides for an integrated circuit (IC) bus system. A local IC is coupled to a remote IC through a bus interface. A local memory is coupled to the local IC. A bus interface controller is employable to track data transfer requests from the remot... | 10/17/2006 |
| 7124323 | Method, system, and program for recovery of a reverse restore operation Disclosed is a technique for processing interruption of an operation that transfers data between a source and a target. An indication that a reverse restore operation has been interrupted is received. It is determined whether designation of at least one of an origin... | 10/17/2006 |
| 7124254 | Method and structure for monitoring pollution and prefetches due to speculative accesses A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two types of events are tracked in one of two different ways: first by coun... | 10/17/2006 |
| 7124236 | Microprocessor including bank-pipelined cache with asynchronous data blocks A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality... | 10/17/2006 |
| 7120723 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 10/10/2006 |
| 7120727 | Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr... | 10/10/2006 |
| 7120743 | Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to t... | 10/10/2006 |
| 7120746 | Technique for data transfer Disclosed is a system, method, and program for transferring data. When a transaction commits, multiple data objects that have been changed by the transaction are identified. The multiple data objects are written from local storage to a cache structure using a batch ... | 10/10/2006 |
| 7120761 | Multi-port memory based on DRAM core A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports. ... | 10/10/2006 |
| 7120651 | Maintaining a shared cache that has partitions allocated among multiple nodes and a data-to-partition mapping Various techniques are described for improving the performance of a multiple node system by allocating, in two or more nodes of the system, partitions of a shared cache. A mapping is established between the data items managed by the system, and the various partition... | 10/10/2006 |
| 7117390 | Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture This invention relates to system architectures, specifically failure-tolerant and self-reconfiguring embedded system architectures. The invention provides both a method and architecture for redundancy. There can be redundancy in both software and hardware for multip... | 10/03/2006 |
| 7117342 | Implicitly derived register specifiers in a processor A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined ... | 10/03/2006 |
| 7116241 | Removable memory cartridge system for use with a server or other processor-based device A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to ... | 10/03/2006 |
| 7116673 | Queue pair resolution in infiniband fabrics A method for determining parameters needed to communicate with a remote node in a computer network is provided. The invention comprises determining the location of the remote node to which an InfiniBand (IB) node might desire to communicate. This resolution comprise... | 10/03/2006 |
| 7117316 | Memory hub and access method having internal row caching A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the mem... | 10/03/2006 |
| 7117308 | Hypertransport data path protocol A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer... | 10/03/2006 |
| 7114056 | Local and global register partitioning in a VLIW processor A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the pluralit... | 09/26/2006 |
| 7114036 | Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each ... | 09/26/2006 |
| 7111146 | Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a vi... | 09/19/2006 |
| 7111129 | Method and system for coherently caching I/O devices across a network The cache keeps regularly accessed disk I/O data within RAM that forms part of a computer systems main memory. The cache operates across a network of computers systems, maintaining cache coherency for the disk I/O devices that are shared by the multiple computer sys... | 09/19/2006 |
| 7107408 | Methods and apparatus for speculative probing with early completion and early request According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether spec... | 09/12/2006 |
| 7107409 | Methods and apparatus for speculative probing at a request cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller associated with a first cluster of processors can determine whether spe... | 09/12/2006 |
| 7107405 | Writing cached data to system management memory In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evict... | 09/12/2006 |
| 7107410 | Exclusive status tags The disclosed embodiments relate to exclusive status tags. A multiprocessor computer system may include multiple processors and caches that may be managed by a directory or snooping. To optimize the performance of the system, the status and ownership information of ... | 09/12/2006 |
| 7106611 | Wavelength division multiplexed memory module, memory system and method A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the... | 09/12/2006 |
| 7106648 | X-address extractor and memory for high speed operation The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is inpu... | 09/12/2006 |
| 7107415 | Posted write buffers and methods of posting write requests in memory modules A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are al... | 09/12/2006 |
| 7103720 | Shader cache using a coherency protocol Methods and systems for caching graphics data using dedicated level one caches and a shared level two cache are described. Furthermore, each method includes a protocol for maintaining coherency between the level one caches and between the level one caches and the le... | 09/05/2006 |
| 7103736 | System for repair of ROM programming errors or defects A system is disclosed for use of imperfect ROMs in embedded systems. The ROM or other memory accessible upon start-up of the system, includes a stored program which checks an external source to determine whether any of the information in the ROM should be replaced. ... | 09/05/2006 |
| 7103737 | Flexible hierarchy of relationships and operations in data volumes Disclosed is an apparatus or method performed by a computer system for creating a hierarchy of data volumes. Each data volume in the hierarchy is a point-in-time (PIT) copy of another data volume in the hierarchy or a PIT copy of a data volume V. In one embodiment o... | 09/05/2006 |
| 7103636 | Methods and apparatus for speculative probing of a remote cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or ... | 09/05/2006 |
| 7103685 | Bitstream compression with don't care values A method and system for processing a plurality of multi-bit configuration words for configuring a programmable logic device. One or more of bits of the multi-bit configuration words are identified as “Don't Care” configuration bits that do not affect the functio... | 09/05/2006 |
| 7103725 | Methods and apparatus for speculative probing with early completion and delayed request According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether spec... | 09/05/2006 |
| 7100001 | Methods and apparatus for cache intervention Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “ex... | 08/29/2006 |
| 7099993 | Multi-level caching in data storage devices A multi-level caching scheme for use in managing the storage of data on a data storage device is disclosed. The data is received by the data storage device as part of a write command issued by the sending interface and specifying one or more particular location(s) o... | 08/29/2006 |
| 7096323 | Computer system with processor cache that stores remote cache presence information A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data mapped to another node are being remotely cached. Rather than storing ... | 08/22/2006 |
| 7096320 | Computer performance improvement by adjusting a time used for preemptive eviction of cache entries A cache memory system can determine that an entry is stale if the entry has not been accessed or modified for a predetermined time. If an entry is stale, the entry may be preemptively evicted. The predetermined time is made dynamically variable. A computer system ca... | 08/22/2006 |
| 7093081 | Method and apparatus for identifying false cache line sharing A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each ... | 08/15/2006 |
| 7089374 | Selectively unmarking load-marked cache lines during transactional program execution One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering access... | 08/08/2006 |
