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| Number | Title | Issue Date |
| 4493026 | Set associative sector cache A cache memory for a data processing system having a tag array in which each tag word represents a predetermined plurality or block group of consecutively addressable data block locations in a data array. The lower order set address bits concurrently acce... | 01/08/1985 |
| 4484267 | Cache sharing control in a multiprocessor The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC... | 11/20/1984 |
| 4471430 | Encachement apparatus Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second ca... | 09/11/1984 |
| 4471429 | Apparatus for cache clearing A cache clearing apparatus for a multiprocessor data processing system having a cache unit and a duplicate directory associated with each processor. The duplicate directory, which reflects the contents of the cache directory within its associated cache un... | 09/11/1984 |
| 4410946 | Cache extension to processor local storage The disclosure pertains to a relatively small local storage (LS) in a processor's IE which can be effectively expanded by utilizing a portion of a processor's store-in-cache. The cache allocates a line (i.e. block) for LS use by the instruction unit sendi... | 10/18/1983 |
| 4410944 | Apparatus and method for maintaining cache memory integrity in a shared memory environment A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor ... | 10/18/1983 |
| 4322815 | Hierarchical data storage system A cache store is provided in conjunction with a main store. Each location of the cache has a changed bit. A list is maintained of the addresses of those locations in the cache store which have been modified. When the list becomes full, the entry at the he... | 03/30/1982 |
| 4197580 | Data processing system including a cache memory A data processing system includes a memory arrangement comprising a main memory, and a cache memory including a validity bit per storage location to indicate the validity of data stored therein. Cache performance is improved by a special read operation to... | 04/08/1980 |
| 4142234 | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor,... | 02/27/1979 |
