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| Number | Title | Issue Date |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370152 | Memory controller with prefetching capability A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodimen... | 05/06/2008 |
| 7370154 | Method and apparatus for maintaining coherence information in multi-cache systems A method and apparatus for maintaining coherence information in multi-cache systems is described herein. In one embodiment, the apparatus includes an Ingrained Sharing Directory Cache (ISDC) to store state information about recent copies of local memory blocks. The ... | 05/06/2008 |
| 7366847 | Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidat... | 04/29/2008 |
| 7366845 | Pushing of clean data to one or more processors in a system having a coherency protocol Techniques for pushing data to multiple processors in a clean state. ... | 04/29/2008 |
| 7366844 | Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single upda... | 04/29/2008 |
| 7366846 | Redirection of storage access requests Provided are a method, system, and article of manufacture, wherein a controller receives a request from one of a plurality of hosts. The controller determines whether a primary storage control unit coupled to the controller is operational. A response is generated by... | 04/29/2008 |
| 7366848 | Reducing resource consumption by ineffective write operations in a shared memory system In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning processing unit requests data from a shared memory location owned by a... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363435 | System and method for coherence prediction A coherence prediction mechanism includes a synchronization manager and a plurality of access predictors. The synchronization manager maintains one or more sequence entries, each sequence entry indicating a sequence in which a corresponding data block is accessed by... | 04/22/2008 |
| 7362772 | Network processing pipeline chipset for routing and host packet processing A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NP... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7363433 | Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ... | 04/22/2008 |
| 7363432 | Method and apparatus for directory-based coherence with distributed directory management A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data... | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7360028 | Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The instruction is received and executed. After the instruction space is... | 04/15/2008 |
| 7360032 | Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache ... | 04/15/2008 |
| 7360023 | Method and system for reducing power consumption in a cache memory A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of bloc... | 04/15/2008 |
| 7360069 | Systems and methods for executing across at least one memory barrier employing speculative fills Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills... | 04/15/2008 |
| 7360033 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can ... | 04/15/2008 |
| 7360060 | Using IMPDEP2 for system commands related to Java accelerator hardware A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determ... | 04/15/2008 |
| 7360031 | Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O ag... | 04/15/2008 |
| 7360021 | System and method for completing updates to entire cache lines with address-only bus operations A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits o... | 04/15/2008 |
| 7360022 | Synchronizing an instruction cache and a data cache on demand In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instr... | 04/15/2008 |
| 7356713 | Method and apparatus for managing the power consumption of a data processing system A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a... | 04/08/2008 |
| 7356651 | Data-aware cache state machine A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the bottleneck to storage. The data-aware cache differentiates and manages dat... | 04/08/2008 |
| 7356650 | Cache apparatus and method for accesses lacking locality Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a ... | 04/08/2008 |
| 7353341 | System and method for canceling write back operation during simultaneous snoop push or snoop kill operation in write back caches A cache write back operation, write back modified data to memory from cache data array to fix inconsistency between them can be cancelled by the results of a comparison of the progress between a write back and snoop push or snoop kill operation. Write back is intend... | 04/01/2008 |
| 7353319 | Method and apparatus for segregating shared and non-shared data in cache memory banks In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated f... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7353344 | Storage device The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas q... | 04/01/2008 |
| 7350033 | Methods and systems for providing validity logic Systems and methods are disclosed for providing validity logic. The disclosed systems and methods may include receiving at least one data value, determining validity data corresponding to the received at least one data value, and providing the validity data correspo... | 03/25/2008 |
| 7350025 | System and method for improved collection of software application profile data for performance optimization The present invention is directed to a system and method for improved collection of application profile data for performance optimization. The invention provides a mechanism for storing usage bits within the hardware cache of a computing device. These usage bits pro... | 03/25/2008 |
| 7350027 | Architectural support for thread level speculative execution A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread s... | 03/25/2008 |
| 7350032 | Cache coherency protocol including generic transient states In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a r... | 03/25/2008 |
| 7346735 | Virtualized load buffers A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information w... | 03/18/2008 |
| 7343395 | Facilitating resource access using prioritized multicast responses to a discovery request Systems and methods are provided to facilitate resource access using prioritized multicast responses to a discovery request. ... | 03/11/2008 |
| 7343464 | Storage controller and storage system Provided is a storage controller having at least one or more first logical devices to be accessed by the host system, and at least one or more virtual devices for connecting the first logical devices and one or more storage devices. At least one of the virtual devic... | 03/11/2008 |
| 7340652 | Invalidation of storage control unit cache metadata Method, apparatus and program product are provided for the invalidation of faulty metadata in a storage controller coupled to a host device. Faulty metadata may include metadata which no longer matches the associated customer data tracks stored on a DASD or other st... | 03/04/2008 |
