Celebrity Inventors
Lawrence Welk, the bandleader who entertained millions of Americans over a generation of broadcasting his TV show, once received a patent: for a music-themed design of an ashtray.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7069391 | Method for improved first level cache coherency A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalid... | 06/27/2006 |
| 7065540 | Managing checkpoint queues in a multiple node system Techniques are provided for managing caches in a system with multiple caches that may contain different copies of the same data item. Specifically, techniques are provided for coordinating the write-to-disk operations performed on such data items to ensure that olde... | 06/20/2006 |
| 7065613 | Method for reducing access to main memory using a stack cache The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area... | 06/20/2006 |
| 7062613 | Methods and apparatus for cache intervention Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds ... | 06/13/2006 |
| 7062611 | Dirty data protection for cache memories A method is described for protecting dirty data in cache memories in a cost-effective manner. When an instruction to write data to a memory location is received, and that memory location is being cached, the data is written to a plurality of cache lines, which are r... | 06/13/2006 |
| 7062675 | Data storage cache system shutdown scheme In a storage system including a write-back cache, dirty data can be flushed from the cache while a controller continues to service host I/O requests. A controller is capable of flushing all the dirty data in the cache to a storage device in response to an indication... | 06/13/2006 |
| 7062612 | Updating remote locked cache A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the... | 06/13/2006 |
| 7058765 | Processor with a split stack Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be i... | 06/06/2006 |
| 7055023 | Apparatus and method for branch prediction where data for predictions is selected from a count in a branch history table or a bias in a branch target buffer An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a histo... | 05/30/2006 |
| 7055006 | System and method for blocking cache use during debugging A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to... | 05/30/2006 |
| 7051223 | System, apparatus, and method for limiting non-volatile memory An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module ... | 05/23/2006 |
| 7051159 | Method and system for cache data fetch operations A cache controller structure and method are provided for managing cache access for a computer system. The computer system has a processor having a direction flag and configured to run a repetitive string operation, wherein the string operation is configured to seque... | 05/23/2006 |
| 7051166 | Directory-based cache coherency scheme for reducing memory bandwidth loss A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a plurality of memory modules storing a plurality of cache lines, with each c... | 05/23/2006 |
| 7051181 | Caching for context switching applications Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage ... | 05/23/2006 |
| 7046250 | Caching fonts for improved bandwidth of transmitted text Caching fonts on a display computer may be performed in order to reduce network bandwidth utilization and/or to improve CPU usage. Text commands may be recorded when they are executed to create a portion of a graphics image. These text commands may be used to update... | 05/16/2006 |
| 7047341 | Multi-processing memory duplication system Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor r... | 05/16/2006 |
| 7047351 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 05/16/2006 |
| 7047371 | Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals fo... | 05/16/2006 |
| 7047363 | Cache memory and control method thereof A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises a tag memory 1 for storing an address tag of an address of a c... | 05/16/2006 |
| 7047379 | Autonomic link optimization through elimination of unnecessary transfers Disclosed are a system, a method, and a computer program product to efficiently create consistent transaction sets to maintain one or more copies of data at different data storage sites. All transactions sent to a primary backup appliance during a consistent transac... | 05/16/2006 |
| 7043609 | Method and apparatus for protecting a state associated with a memory structure A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state information is identified from the state information. Next, a copy of the c... | 05/09/2006 |
| 7043610 | System and method for maintaining cache coherency without external controller intervention A disk array includes a system and method for cache management and conflict detection. Incoming host commands are processed by a storage controller, which identifies a set of at least one cache segment descriptor (CSD) associated with the requested address range. Co... | 05/09/2006 |
| 7039762 | Parallel cache interleave accesses with address-sliced directories A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split... | 05/02/2006 |
| 7035974 | RAID-5 disk having cache memory implemented using non-volatile RAM A computer implemented cache memory for a RAID-5 configured disk storage system to achieve a significant enhancement of the data access and write speed of the raid disk. A memory cache is provided between the RAID-5 controller and the RAID-5 disks to speed up RAID-5... | 04/25/2006 |
| 7035981 | Asynchronous input/output cache having reduced latency The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device in... | 04/25/2006 |
| 7035908 | Method for multiprocessor communication within a shared memory architecture An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pas... | 04/25/2006 |
| 7035979 | Method and apparatus for optimizing cache hit ratio in non L1 caches A method and apparatus for increasing the performance of a computing system and increasing the hit ratio in at least one non-L1 cache. A caching assistant and a processor are embedded in a processing system. The caching assistant analyzes system activity, monitors a... | 04/25/2006 |
| 7030878 | Method and apparatus for generating a shadow effect using shadow volumes The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil... | 04/18/2006 |
| 7028144 | Method and apparatus for an in-situ victim cache A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose... | 04/11/2006 |
| 7027042 | Display apparatus and error detection method thereof A display apparatus includes a first video signal processing part which processes a video signal output from a video card provided in a computer main body and displays a picture thereof, a picture data storing part, and an error detecting part which captures the vid... | 04/11/2006 |
| 7028150 | Arrangement of data within cache lines so that tags are first data received A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code porti... | 04/11/2006 |
| 7027064 | Active block write-back from SRAM cache to DRAM An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes ... | 04/11/2006 |
| 7028151 | Information processing device equipped with improved address queue register files for cache miss When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input addre... | 04/11/2006 |
| 7028299 | Task-based multiprocessing system An embodiment of the present invention is a task manager to manage tasks in a multiprocessor system. A task table stores task entries corresponding to tasks executed by at least one processor. A block allocation circuit allocates blocks of the cache memory used by t... | 04/11/2006 |
| 7024521 | Managing sparse directory evictions in multiprocessor systems via memory locking Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is assoc... | 04/04/2006 |
| 7024520 | System and method enabling efficient cache line reuse in a computer system A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing th... | 04/04/2006 |
| 7020746 | Method and system for an atomically updated, central cache memory Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data in the cache, accessing the data through a reference table. Applicat... | 03/28/2006 |
| 7020752 | Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of s... | 03/28/2006 |
| 7017014 | Method, system and program product for maintaining data consistency across a hierarchy of caches A method, system and program product maintains consistency of data across a hierarchy of caches. Under the present invention, each data entry in the hierarchy of caches is assigned its own dependency identifier as well as the dependency identifiers of any data entri... | 03/21/2006 |
| 7017025 | Mechanism for proxy management of multiprocessor virtual memory A method and apparatus within a computer processing environment is provided for proxy management of a plurality of memory management units connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system inclu... | 03/21/2006 |
