Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7676637 | Location-aware cache-to-cache transfers In shared-memory multiprocessor systems, cache interventions from different sourcing caches can result in different cache intervention costs. With location-aware cache coherence, when a cache receives a data request, the cache can determine whether sourcing the data... | 03/09/2010 |
| 7620779 | System and method for handling direct memory accesses Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known ... | 11/17/2009 |
| 7620778 | Low power microprocessor cache memory and method of operation Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memor... | 11/17/2009 |
| 7613884 | Multiprocessor system and method ensuring coherency between a main memory and a cache memory A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a copy of a part of a memory region group of the main memory of one node. ... | 11/03/2009 |
| 7606980 | Demand-based error correction A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performanc... | 10/20/2009 |
| 7584329 | Data processing system and method for efficient communication utilizing an Ig coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a me... | 09/01/2009 |
| 7581067 | Load when reservation lost instruction for performing cacheline polling A load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process the... | 08/25/2009 |
| 7558923 | Prevention of live-lock in a multi-processor system Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to... | 07/07/2009 |
| 7555611 | Memory management of local variables upon a change of context A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory pref... | 06/30/2009 |
| 7523267 | Method for ensuring fairness among requests within a multi-node computer system A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed... | 04/21/2009 |
| 7509461 | Method and apparatus for intelligent buffer cache pre-emption The present invention augments each entry in a memory frame table to include information associated with the availability of any page that is buffer cache allocated. The availability information may include, for example, a link to a buffer cache descriptor associate... | 03/24/2009 |
| 7502894 | Shared rowset Multiple Shared Rowsets, can access rows of data stored in a Cached Rowset independently. These Shared Rowsets can have their own cursor, sorted order, filtered rows, and pending changes. ... | 03/10/2009 |
| 7496715 | Programmable cache management system and method A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control i... | 02/24/2009 |
| 7493453 | System, method and storage medium for prefetching via memory block tags A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag i... | 02/17/2009 |
| 7487299 | Cache memory to support a processor's power mode of operation A system, method, and apparatus for a cache memory to support a low power mode of operation. ... | 02/03/2009 |
| 7484044 | Method and apparatus for joint cache coherency states in multi-interface caches A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for... | 01/27/2009 |
| 7480772 | Data processing system and method for efficient communication utilizing an Tn and Ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a r... | 01/20/2009 |
| 7478203 | Technique for eliminating dead stores in a processor A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the... | 01/13/2009 |
| 7475196 | Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache mem... | 01/06/2009 |
| 7472231 | Storage area network data cache A cache connected to the virtualization engine in the center of a storage area network. The invention caches data in a virtual cache, without requiring translation to the physical location. The cache is done as the data crosses the network through the virtualization... | 12/30/2008 |
| 7464227 | Method and apparatus for supporting opportunistic sharing in coherent multiprocessors A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment... | 12/09/2008 |
| 7454577 | Data processing system and method for efficient communication utilizing an Tn and Ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a r... | 11/18/2008 |
| 7454578 | Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an oper... | 11/18/2008 |
| 7444476 | System and method for code and data security in a semiconductor device A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the d... | 10/28/2008 |
| 7434007 | Management of cache memories in a data processing apparatus The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing d... | 10/07/2008 |
| 7428617 | Cache memory and method to maintain cache-coherence between cache memory units A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-l... | 09/23/2008 |
| 7426627 | Selective address translation for a resource such as a hardware device A computing system has a resource for providing resource services, where each resource service is accessed by way of a system address (SA). A device requests the resource services of the resource by way of requests, where each request includes a remote address (RA) ... | 09/16/2008 |
| 7426626 | TLB lock indicator A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access ... | 09/16/2008 |
| 7421624 | Data recovery apparatus and method used for flash memory A data recovery apparatus and method used for a flash memory, which can recover data damaged or lost when power supplied to the flash memory is cut off while data operations are being consecutively performed on at least one data stored in the flash memory. The data ... | 09/02/2008 |
| 7418547 | System and method to protect data stored in a storage system In an example of an embodiment of the invention, a method is provided for recording data transmitted to a storage system, wherein the storage system has a cache and at least one storage device, and the data comprises initial data items that are transmitted to the st... | 08/26/2008 |
| 7418558 | Information processing system, system control apparatus, and system control method A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received extern... | 08/26/2008 |
| 7418526 | Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses ... | 08/26/2008 |
| 7415577 | Method and apparatus to write back data Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in response to a change in address mapping to indicate that the block of data ... | 08/19/2008 |
| 7412569 | System and method to track changes in memory Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a trackin... | 08/12/2008 |
| 7412567 | Value-based memory coherence support In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is... | 08/12/2008 |
| 7401185 | Buffered indexing to manage hierarchical tables Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the reques... | 07/15/2008 |
| 7398377 | Apparatus and method for target address replacement in speculative branch target address cache An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used... | 07/08/2008 |
| 7395373 | Set-associative cache using cache line decay counts and set overflow Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss occurs within the primary set, a cache line from the primary set is select... | 07/01/2008 |
| 7395379 | Methods and apparatus for responding to a request cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluste... | 07/01/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |