Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 6510495 | Data write method into nonvolatile memory, information processing device and recording medium A method for writing data into a nonvolatile memory that allows data deletion in block units includes the steps of storing the identification information of a block to which data stored in a cache memory belongs, and, when writing data into the nonvolatil... | 01/21/2003 |
| 6502172 | Memory accessing and controlling unit A memory accessing and controlling unit that controls the transfer of data between a CPU and a memory cluster. The memory accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU interface circuit pic... | 12/31/2002 |
| 6496905 | Write buffer with burst capability Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an addres... | 12/17/2002 |
| 6490657 | Cache flush apparatus and computer system having the same Addresses of all of dirty blocks of a cache memory are, by an update address registering section, stored in one of plural regions of an update address memory. When a certain cache block is brought to a dirty state and then suspended from the dirty state, ... | 12/03/2002 |
| 6490655 | Data processing apparatus and method for cache line replacement responsive to the operational state of memory A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache stora... | 12/03/2002 |
| 6484242 | Cache access control system A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plu... | 11/19/2002 |
| 6477622 | Simplified writeback handling The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e.g., for a cache miss, dirty data in the main cache is merged with modifi... | 11/05/2002 |
| 6457101 | System and method for providing the speculative return of cached data within a hierarchical memory system A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second stora... | 09/24/2002 |
| 6449707 | Information processing unit, information processing structure unit, information processing structure, memory structure unit and semiconductor memory device A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output secti... | 09/10/2002 |
| 6446172 | Method and system for controlling the memory access operation performed by a central processing unit in a computer system A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method ... | 09/03/2002 |
| 6446145 | Computer memory compression abort and bypass mechanism when cache write back buffer is full In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for enabling termination of a pending compression opera... | 09/03/2002 |
| 6438657 | Pipelined snooping of multiple L1 cache lines A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cach... | 08/20/2002 |
| 6438660 | Method and apparatus for collapsing writebacks to a memory for resource efficiency Method and apparatus are disclosed which increase resource efficiency by collapsing writebacks to a memory. In general the method and apparatus receive an address of a memory request and compare that address to addresses of writebacks stored in a memory c... | 08/20/2002 |
| 6438658 | Fast invalidation scheme for caches A method and apparatus for single cycle, cache line invalidation within a cache memory is described. The method includes enabling memory cells within a cache state array of the cache memory. An invalid state is then written to each memory cell within the ... | 08/20/2002 |
| 6434677 | Method and apparatus for altering data length to zero to maintain cache coherency Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within... | 08/13/2002 |
| 6434433 | External components for a microprocessor system for control of plural control elements and operating method The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element... | 08/13/2002 |
| 6434673 | Optimized configurable scheme for demand based resource sharing of request queues in a cache controller A method is provided that includes a step for setting a maximum number of concurrently allocated queue entries to service writeback evictions. The method also includes a step of setting a register bit based on cache requests. The method also includes a st... | 08/13/2002 |
| 6430657 | COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK Atomic memory operations are provided by using exportable "fetch and add" instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-3... | 08/06/2002 |
| 6425050 | Method, system, and program for performing read operations during a destage operation Disclosed is a method, system, and program for processing data access requests, such as read requests, to a storage location maintained in both a first storage, such as a cache, area and second storage area, such as a disk drive, during a destage operatio... | 07/23/2002 |
| 6418514 | Removal of posted operations from cache operations queue A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blo... | 07/09/2002 |
| 6415357 | Caching method and apparatus As copies of data from a main memory are stored in a cache memory of a processor of a computer system as original data, the addresses of those copies are stored successively in a queue. Once the depth of the queue is reached, the storage of each new addre... | 07/02/2002 |
| 6408363 | Speculative pre-flush of data in an out-of-order execution processor system Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of... | 06/18/2002 |
| 6405288 | Method and system for controlling the memory access operation by central processing unit in a computer system A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner. This memory access control method and system is chara... | 06/11/2002 |
| 6401172 | Recycle mechanism for a processing agent A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a pending external transaction, canceling and recycling the dat... | 06/04/2002 |
| 6401175 | Shared write buffer for use by multiple processor units A shared write back buffer for storing data from a data cache to be written back to memory. The shared write back buffer includes a plurality of ports, each port being associated with one of a plurality of processing units. All processing units in the plu... | 06/04/2002 |
| 6401163 | Apparatus and method for rewriting data from volatile memory to nonvolatile memory In an electronic control system having a CPU, a RAM and an EEPROM, an original data stored in the EEPROM is written into the RAM to be updated in a control calculation processing of the CPU. If the updated data is the type which is to be written back into... | 06/04/2002 |
| 6397305 | Method and apparatus for controlling shared memory access A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores words prior to writing them in the common memory, and a c... | 05/28/2002 |
| 6393529 | Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write A messaging scheme that conserves system memory bandwidth and maintains cache coherency during a victim block write operation in a multiprocessing computer system is described. A source node having a dirty victim cache block--a modified cache block that i... | 05/21/2002 |
| 6385703 | Speculative request pointer advance for fast back-to-back reads A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the ... | 05/07/2002 |
| 6378055 | Memory accessing and controlling method A memory accessing and controlling unit that controls the transfer of data between a CPU and a memory cluster. The memory accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU interface circuit pic... | 04/23/2002 |
| 6373779 | Block RAM having multiple configurable write modes for use in a field programmable gate array A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality ... | 04/16/2002 |
| 6366984 | Write combining buffer that supports snoop request A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store ... | 04/02/2002 |
| 6360298 | Load/store instruction control circuit of microprocessor and load/store instruction control method A load/store instruction control method of a microprocessor according to the present invention has a feature as follows. The circuit implements non-blocking cache which does not allow a pipeline process of a microprocessor to stop even if a cache miss by ... | 03/19/2002 |
| 6360301 | Coherency protocol for computer cache A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line in the special state is evicted from the lower level cache... | 03/19/2002 |
| 6353876 | Cache memory exchange optimized memory organization for a computer system Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the s... | 03/05/2002 |
| 6353875 | Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions Upon snooping a combined data access and castout/deallocate operation initiating by a horizontal storage device, snoop logic determines, from coherency state information appended to either the combined operation or the combined response to the operation, ... | 03/05/2002 |
| 6351790 | Cache coherency mechanism A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated therewith. The computer system includes a memory that provid... | 02/26/2002 |
| 6349367 | Method and system for communication in which a castout operation is cancelled in response to snoop responses An effectively "conditional", cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU positi... | 02/19/2002 |
| 6345320 | DMA address buffer and cache-memory control system A system includes a main-memory unit, an input/output-control unit which performs a write operation with respect to the main-memory unit by way of direct memory access, and a central-control unit which operates based on information stored in the main-memo... | 02/05/2002 |
| 6345339 | Pseudo precise I-cache inclusivity for vertical caches A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which deno... | 02/05/2002 |
