Bizarre Patents
Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 5045996 | Multiprocessor cache memory housekeeping Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a lau... | 09/03/1991 |
| 5043886 | Load/store with write-intent for write-back caches A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also d... | 08/27/1991 |
| 5034885 | Cache memory device with fast data-write capacity A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an ... | 07/23/1991 |
| 5029070 | Coherent cache structures and methods A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand ca... | 07/02/1991 |
| 4992977 | Cache memory device constituting a memory device used in a computer A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cach... | 02/12/1991 |
| 4933837 | Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to the invention, the memory system stores preselected instruct... | 06/12/1990 |
| 4924379 | Multiprocessor system with several processors equipped with cache memories and with a common memory In such a multiprocessor, in which the common memory (M) or one of the cache memories (C1, C2) can be owner of a variable determined by its address and in which it is always only the owner of a variable which delivers it to the bus (1) following a read re... | 05/08/1990 |
| 4858111 | Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache A computer system in which only the cache memory is permitted to communicate with main memory and the same address being used in the cache is also sent at the same time to the main memory. Thus, as soon as it is discovered that the desired main memory add... | 08/15/1989 |
| 4847804 | Apparatus and method for data copy consistency in a multi-cache data processing unit In a multi-processor unit data processing system, apparatus and method are described for providing that only the most recent version of any data signal group will be available for manipulation by a requesting data processing unit. A "multiple" state for a... | 07/11/1989 |
| 4811203 | Hierarchial memory system with separate criteria for replacement and writeback without replacement In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to s... | 03/07/1989 |
| 4530055 | Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor pa... | 07/16/1985 |
| 4523206 | Cache/disk system with writeback regulation relative to use of cache memory In a system having a cache memory and a bulk memory, and wherein a command queue is maintained for storing commands waiting to be executed, each command is assigned a priority level for execution vis-a-vis other commands in the queue. Commands are generat... | 06/11/1985 |
| 4429363 | Method and apparatus for managing data movements from a backing store to a caching buffer store In a storage hierarchy, promotion of data from a backing store to a caching buffer store is restricted based upon status of the cache and activity of a last storage reference. Observed writing activity selectively inhibits data promotion. Data promotion o... | 01/31/1984 |
| 4399506 | Store-in-cache processor means for clearing main storage Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS). Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruc... | 08/16/1983 |
| 4345309 | Relating to cached multiprocessor system with pipeline timing A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds t... | 08/17/1982 |
| 4317168 | Cache organization enabling concurrent line castout and line fetch transfers with main storage A cache organization that enables many cache functions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the processor technology. Main storage has a data bus-out and a data bus-in, each tran... | 02/23/1982 |
| 4084231 | System for facilitating the copying back of data in disc and tape units of a memory hierarchial system This is a multi level or hierarchial memory system for a multi processing system in which two or more processing units access the memory system. This memory system has two types of memory units on each level with the exception of the lowest level. One of ... | 04/11/1978 |
| 4077059 | Multi-processing system with a hierarchial memory having journaling and copyback This is a hierarchial memory system for a multi-processing system which has two or more processing units accessing the memory system. The memory system has two different types of memory units on each level. One of the types of units is called the data sto... | 02/28/1978 |
| 4020466 | Memory hierarchy system with journaling and copy back This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that da... | 04/26/1977 |
