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| Number | Title | Issue Date |
| 8176261 | Information processing apparatus and data transfer method One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manage... | 05/08/2012 |
| 8151062 | Consistency models in a distributed store Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setti... | 04/03/2012 |
| 8151061 | Ensuring coherence between graphics and display domains A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. ... | 04/03/2012 |
| 8145848 | Processor and method for writeback buffer reuse A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writ... | 03/27/2012 |
| 8131946 | Converting victim writeback to a fill In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block ... | 03/06/2012 |
| 8127084 | Using different algorithms to destage different types of data from cache Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorith... | 02/28/2012 |
| 8108622 | Memory management system and image processing apparatus A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back o... | 01/31/2012 |
| 8041899 | System and method for fetching information to a cache module using a write back allocate algorithm A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to... | 10/18/2011 |
| 7836262 | Converting victim writeback to a fill In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block ... | 11/16/2010 |
| 7809892 | Asynchronous data replication Technologies are provided herein for asynchronous data replication. A primary server maintains and exposes a storage volume for use by storage clients. The primary server receives write operations directed toward the storage volume and performs the writes on the sto... | 10/05/2010 |
| 7783839 | Using different algorithms to destage different types of data from cache Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorith... | 08/24/2010 |
| 7769960 | Computer program product and a system for a priority scheme for transmitting blocks of data Provided are techniques for transmitting blocks of data. It is determined whether any high priority out of sync (HPOOS) indicator is set to indicate that a number of modified segments associated with a block of data are less than or equal to a modified segments thre... | 08/03/2010 |
| 7769959 | System and method to facilitate ordering point migration to memory A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node ... | 08/03/2010 |
| 7721051 | Techniques to improve cache performance Method and apparatus to improve cache performance using interarrival times between demand requests are described. ... | 05/18/2010 |
| 7716260 | Techniques for transaction semantics for a database server performing file operations A method and apparatus for reverting a resource to a prior state in time is provided. Changes are committed to a resource at a particular point in time. After the particular point in time, a request, which may be a file system operation request, to revert the resour... | 05/11/2010 |
| 7698508 | System and method for reducing unnecessary cache operations A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure... | 04/13/2010 |
| 7636814 | System and method for asynchronous reads of old data blocks updated through a write-back cache A system for asynchronous reads of old data blocks updated through a write-back cache includes a storage device, a write-back cache, a storage consumer, a storage processing node, and device management software. The device management software may be configured to st... | 12/22/2009 |
| 7600080 | Avoiding deadlocks in a multiprocessor system In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the hom... | 10/06/2009 |
| 7574568 | Optionally pushing I/O data into a processor's cache A method, an apparatus and a system for a computing system implements a technique known as cache push that enhances a single writer invalidation protocol with the ability to optionally push data into another processor's cache without changing the memory consistency ... | 08/11/2009 |
| 7555610 | Cache memory and control method thereof The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit 39 which write... | 06/30/2009 |
| 7509460 | DRAM remote access cache in local memory in a distributed shared memory system In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a re... | 03/24/2009 |
| 7496714 | Method and system for adaptive back-off and advance for non-volatile storage (NVS) occupancy level management A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the... | 02/24/2009 |
| 7472230 | Preemptive write back controller A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The preemptive write back controller includes a list of the lines, pages,... | 12/30/2008 |
| 7444476 | System and method for code and data security in a semiconductor device A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the d... | 10/28/2008 |
| 7444478 | Priority scheme for transmitting blocks of data Provided are techniques for transmitting blocks of data. It is determined whether any high priority out of sync (HPOOS) indicator is set to indicate that a number of modified segments associated with a block of data are less than or equal to a modified segments thre... | 10/28/2008 |
| 7441081 | Write-back caching for disk drives Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In o... | 10/21/2008 |
| 7418533 | Data storage system and control apparatus with a switch unit connected to a plurality of first channel adapter and modules wherein mirroring is performed A storage system has a plurality of control modules for controlling a storage device for accesses from a mainframe host and an open system host respectively supporting different protocols. An open channel adaptor and a mainframe channel adaptor are separately provid... | 08/26/2008 |
| 7415577 | Method and apparatus to write back data Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in response to a change in address mapping to indicate that the block of data ... | 08/19/2008 |
| 7415576 | Data processor with block transfer control A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible int... | 08/19/2008 |
| 7406566 | Ring interconnect with multiple coherence networks A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each commu... | 07/29/2008 |
| 7397478 | Various apparatuses and methods for switching between buffers using a video frame buffer flip queue A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded in... | 07/08/2008 |
| 7395377 | Method and system for adaptive back-off and advance for non-volatile storage (NVS) occupancy level management A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the... | 07/01/2008 |
| 7394817 | Distributed data caching in hybrid peer-to-peer systems A method for caching data in a hybrid peer-to-peer system comprising a plurality of interconnected peer computers is disclosed. The method comprising the steps of establishing (1702) a performance criterion, arranging (1703) the hybrid peer-to-peer sys... | 07/01/2008 |
| 7392352 | Computer architecture for shared memory access A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting ... | 06/24/2008 |
| 7389387 | Distributed memory module cache writeback One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 06/17/2008 |
| 7389383 | Selectively unmarking load-marked cache lines during transactional program execution One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering access... | 06/17/2008 |
| 7386659 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 06/10/2008 |
| 7386682 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is disp... | 06/10/2008 |
| 7386681 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/r... | 06/10/2008 |
| 7380069 | Method and apparatus for DMA-generated memory write-back A method for memory write-back provides a memory access controller and then generates a write-back pattern in the memory access controller. The write-back pattern is then written back into a memory starting at a predetermined address location and continuing for a pr... | 05/27/2008 |
