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| Number | Title | Issue Date |
| 8117400 | System and method for fetching an information unit A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a h... | 02/14/2012 |
| 7877550 | Bus controller initiated write-through mechanism with hardware automatically generated clean command A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previousl... | 01/25/2011 |
| 7774554 | System and method for intelligent software-controlled cache injection A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be wri... | 08/10/2010 |
| 7472229 | Bus controller initiated write-through mechanism A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previousl... | 12/30/2008 |
| 7386681 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/r... | 06/10/2008 |
| 7386682 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is disp... | 06/10/2008 |
| 7376789 | Wide-port context cache apparatus, systems, and methods Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for e... | 05/20/2008 |
| 7376799 | System for reducing the latency of exclusive read requests in a symmetric multi-processing system A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with all of the cell boards being connected to at least one crossbar switch.... | 05/20/2008 |
| 7363540 | Transaction-safe FAT file system improvements Concepts for enhancing operation of transaction-safe file allocation table systems are described. The concepts include writing a file to non-volatile memory media and rendering an update of file size to the TFAT storage medium; and receiving a request to locate data... | 04/22/2008 |
| 7360031 | Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O ag... | 04/15/2008 |
| 7356651 | Data-aware cache state machine A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the bottleneck to storage. The data-aware cache differentiates and manages dat... | 04/08/2008 |
| 7353342 | Shared lease instruction support for transient blocking synchronization A computer system implementing transient blocking synchronization allows a memory location leased by a first process to be read-accessible to another process. In other words, more than one thread may have read-only type leases on a given memory location at a given t... | 04/01/2008 |
| 7343619 | Trusted flow and operation control method The objective of this invention is to ensure that programs that generate and send data packets are well behaved. This invention discloses a method and system that consist of an end station and a network interface, such that, the network interface is capable of deter... | 03/11/2008 |
| 7340563 | Data transmission device having the shape of a standard 3.5″ disk A data transmission device includes a memory cache table (4) composed of a DRAM memory, a standard 2.5″ hard disk (5), a control CPU (7), a FPGA (6) (or ASIC), a disk interface (3) and a backup battery. The device is unitized in ... | 03/04/2008 |
| 7340568 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 03/04/2008 |
| 7330940 | Method and system for cache utilization by limiting prefetch requests System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a number of pending memory requests for the entity is less than a pref... | 02/12/2008 |
| 7330911 | Accessing a memory using a plurality of transfers A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in... | 02/12/2008 |
| 7328310 | Method and system for cache utilization by limiting number of pending cache line requests System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is ... | 02/05/2008 |
| 7318145 | Random slip generator A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the sys... | 01/08/2008 |
| 7313614 | Switching system A system and method for provided a switch system (100) having a first configurable set of processor elements (102) to process storage resource connection requests (104), a second configurable set of processor elements capable of communications w... | 12/25/2007 |
| 7296167 | Combined system responses in a chip multiprocessor In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of processor cores. The node controller is coupled to receive an external reque... | 11/13/2007 |
| 7263580 | Cache flush based on checkpoint timer A data processing system is used which is provided with a computer for executing a program, and a storage unit having a cache memory for storing data transmitted as a result of execution of the program and a disk device for storing data stored in the cache memory. T... | 08/28/2007 |
| 7257677 | Data image cache used in testing The present invention is directed to a system and method of testing using a data image cache. An image server is coupled to one or more test beds to perform testing and/or debug operations on one or more components. Each test bed has one or more test slots to receiv... | 08/14/2007 |
| 7254686 | Switching between mirrored and non-mirrored volumes Provided are a method, system, and article of manufacture, wherein a request is received for switching a logical volume from one state to another state, wherein the logical volume is in a mirrored state if data corresponding to the logical volume is mirrored from a ... | 08/07/2007 |
| 7254678 | Enhanced STCX design to improve subsequent load efficiency A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve op... | 08/07/2007 |
| 7240143 | Data access and address translation for retrieval of data amongst multiple interconnected access nodes A low-latency storage memory system is built from multiple memory units such as high-density random access memory. Multiple access ports provide access to memory units and send the resultant data out interface ports. The memory units communicate with the access port... | 07/03/2007 |
| 7240238 | Remote data mirroring Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly acces... | 07/03/2007 |
| 7237069 | Arrangement and method for update of configuration cache data An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique. This provides the advantage that known changes to the subsystem do... | 06/26/2007 |
| 7234028 | Power/performance optimized cache using memory write prevention through write snarfing A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-bac... | 06/19/2007 |
| 7233880 | Adaptive cache algorithm for temperature sensitive memory A temperature sensitive memory, such as a ferroelectric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In suc... | 06/19/2007 |
| 7231497 | Merging write-back and write-through cache policies In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain emb... | 06/12/2007 |
| 7228385 | Processor, data processing system and method for synchronizing access to data in shared memory A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to... | 06/05/2007 |
| 7219197 | Cache memory, processor and cache control method A cache memory, comprising: a data storage capable of storing data which requires consistency of data with a main memory; and a storage controller which controls to store data which does not require consistency of data with said main memory in an arbitrary data regi... | 05/15/2007 |
| 7216202 | Method and apparatus for supporting one or more servers on a single semiconductor chip One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without... | 05/08/2007 |
| 7200717 | Processor, data processing system and method for synchronizing access to data in shared memory A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit ... | 04/03/2007 |
| 7197604 | Processor, data processing system and method for synchronzing access to data in shared memory A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit.... | 03/27/2007 |
| 7194587 | Localized cache block flush instruction A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective ad... | 03/20/2007 |
| 7185029 | Method and apparatus for maintaining, and updating in-memory copies of the first and second pointers to reference the new versions of the first and second control structures that indicate available and allocated portions of usable space in the data file Method and apparatus for expanding usable space for an application data file. A control file is maintained with control structures that indicate available and allocated portions of usable space in the data file, along with quantities of available space in portions o... | 02/27/2007 |
| 7185150 | Architectures for self-contained, mobile, memory programming A computer system comprising: a plurality of memories each containing one or more locations; and a first threadlet for causing a first program to run in the computer system when at least one first memory location of the plurality of memory locations is local to the ... | 02/27/2007 |
| 7177987 | System and method for responses between different cache coherency protocols Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a conditio... | 02/13/2007 |
