Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7330904 | Communication of control information and data in client/server systems The invention provides a method and system in which a client/server system uses a NUMA communication link, possibly in combination with a byte serial communication link, to transfer relatively large blocks of data between client and server. The method and system pro... | 02/12/2008 |
| 7330937 | Management of stack-based memory usage in a processor A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as eith... | 02/12/2008 |
| 7330963 | Resolving all previous potentially excepting architectural operations before issuing store architectural operation Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may ... | 02/12/2008 |
| 7330911 | Accessing a memory using a plurality of transfers A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in... | 02/12/2008 |
| 7328313 | Methods to perform cache coherency in multiprocessor system using reserve signals and control bits A cache controller prevents the use of data in a write-back cache memory from being propagated except to a client asserting a reserve signal, if a first control bit is set, or until the data is backed-up in a main memory, if a second control bit is set. The control ... | 02/05/2008 |
| 7328222 | Method and apparatus for preserving data coherency in a database by generating a command object that includes instructions for writing a data record to a local cache A method of and system for managing cached data across disparate systems is disclosed. A system for providing cached data coherency includes: a client computer, an application server, a main database, one or more remote application servers, and a communication netwo... | 02/05/2008 |
| 7327749 | Combined buffering of infiniband virtual lanes and queue pairs A system and method for shared buffering of InfiniBand virtual lanes and queue pairs. Instead of allocating dedicated memory space (e.g., a set of FIFO queues), a shared memory dynamically accommodates traffic received on different virtual lanes and/or queue pairs o... | 02/05/2008 |
| 7328331 | Method and system of aligning execution point of duplicate copies of a user program by copying memory stores A method and system of aligning execution point of duplicate copies of a user program by copying memory stores. Some of the exemplary embodiments may be a method comprising aligning the execution point of duplicate copies of a user program executed in a first and se... | 02/05/2008 |
| 7325115 | Encryption of system paging file An operating system copies data from memory pages into a paging file on disk, in order to free up space in the memory. A mechanism is disclosed that causes the data to be encrypted as it is copied into the paging file, thereby protecting the paged data from unauthor... | 01/29/2008 |
| 7325064 | Distributed locking protocol with asynchronous token prefetch and relinquish Asynchronous messages are used to prefetch and/or relinquish tokens used in providing locking of shared resources. A message is sent to prefetch one or more tokens, and prior to receiving a reply for the message, another message (e.g., an acquire) is sent for at lea... | 01/29/2008 |
| 7325101 | Techniques for reducing off-chip cache memory accesses Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cac... | 01/29/2008 |
| 7324995 | Method for retrieving and modifying data elements on a shared medium A method for retrieving and modifying data elements on a shared medium following request from multiple client computers, such that data retrieval transactions on a data element, originating from one or more clients, are not compromised by data update transactions on... | 01/29/2008 |
| 7325102 | Mechanism and method for cache snoop filtering A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a storage including a plurality of entries configured to store corresponding snoop filter indications. The mechanism also includes a cache controller configured receive a transac... | 01/29/2008 |
| 7321956 | Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data... | 01/22/2008 |
| 7320054 | Multiprocessor system having a shared memory Disclosed is a multiprocessor system in which even if contention occurs when a common memory is accessed from each of a plurality of processors, the number of times the common memory is accessed is capable of being reduced. The common memory of the multiprocessor sy... | 01/15/2008 |
| 7320010 | Controlling updates of electronic files In controlling electronic file updates, an upgrade system identifies host device models that include an original electronic file upon receipt of a new file, when the new file is an updated version of the original file. Using the identified model list, the upgrade sy... | 01/15/2008 |
| 7320039 | Method for processing consistent data sets The invention relates to a method for processing consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system. According to the invention, by connecting a communication memory and a consistency, transmission and r... | 01/15/2008 |
| 7318126 | Asynchronous symmetric multiprocessing An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes co... | 01/08/2008 |
| 7318102 | Reliable datagram A reliable datagram service is implemented with a source and destination resource (SDR). Source SDR resources, at a source device, multiplex units of work produced by at least one source application instance (AI) into a serial unit of work stream having units of wor... | 01/08/2008 |
| 7318165 | Apparatus for managing a cache in a distributed caching environment having an event auditor and a cache auditor A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management s... | 01/08/2008 |
| 7315919 | Bandwidth reduction technique in a snooping-based cache-coherent cluster of multiprocessing nodes A cluster of multiprocessing nodes uses snooping-based cache-coherence to maintain consistency among the cache memories of the multiprocessing nodes. One or more of the multiprocessing nodes each maintain a directory table that includes a list of addresses of data l... | 01/01/2008 |
| 7315912 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/01/2008 |
| 7315616 | System and method for maintaining real-time agent information for multi-channel communication queuing An apparatus and method for maintaining data for multi-channel communication queuing associated with different media formats such as telephone, email, and fax. A list of agent data includes information related to types of communication media an agent can access. The... | 01/01/2008 |
| 7310708 | Cache system with groups of lines and with coherency for both single lines and groups of lines In a computer system with caching, memory transactions can retrieve and store groups of lines. Coherency states are maintained for groups of lines, and for individual lines. A single coherency transaction, and a single address transaction, can then result in the tra... | 12/18/2007 |
| 7310709 | Method and apparatus for primary cache tag error handling A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary ... | 12/18/2007 |
| 7308539 | Concurrent read access and exclusive write access to data in shared memory architecture Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission... | 12/11/2007 |
| 7308538 | Scope-based cache coherence With scope-based cache coherence, a cache can maintain scope information for a memory address. The scope information specifies caches in which data of the address is potentially cached, but not necessarily caches in which data of the address is actually cached. Appr... | 12/11/2007 |
| 7305397 | Caching data communications to reduce latency A system for allowing applications to communicate data to a database on a host system run by a system administrator. In one embodiment, the system may perform several caching functions of data passing between a database and a user on a CAD system. ... | 12/04/2007 |
| 7305524 | Snoop filter directory mechanism in coherency shared memory system Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the... | 12/04/2007 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7302527 | Systems and methods for executing load instructions that avoid order violations Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to sear... | 11/27/2007 |
| 7302529 | Method for comparing contents of memory components A method, system, device and software product for comparing the contents of memory components in electronic devices. A data transmission connection is established between the electronic devices, and device identifiers and checksum values are determined in the electr... | 11/27/2007 |
| 7302505 | Receiver multi-protocol interface and applications thereof A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The... | 11/27/2007 |
| 7302492 | Method and apparatus for matching web service in applications using a data object exchange protocol Techniques for matching services of a first server with a second server include storing for a translator process transformation rules. The transformation rules transform between hierarchical elements of messages formatted for the first server and hierarchical elemen... | 11/27/2007 |
| 7301954 | Multiple-buffer queueing of data packets with high throughput rate The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The con... | 11/27/2007 |
| 7296167 | Combined system responses in a chip multiprocessor In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of processor cores. The node controller is coupled to receive an external reque... | 11/13/2007 |
| 7296121 | Reducing probe traffic in multiprocessor systems A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory li... | 11/13/2007 |
| 7296270 | Method and control unit for controlling technical procedures in a motor vehicle A method and a control unit for controlling technical procedures, particularly in a motor vehicle. In the method, a control program of a computing element, particularly a microprocessor, is processed. The control program is subdivided into several tasks and each tas... | 11/13/2007 |
| 7296122 | Flexible probe/probe response routing for maintaining coherency A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches a... | 11/13/2007 |
| 7295619 | Interface for data transmission A system for production and/or processing of data bursts has at least two series-connected modules, with data (Data) and information (Enable) relating to the validity of the data (Data) being transmitted from a first module (A) to an adjacent second module (B), and ... | 11/13/2007 |
