Quotables
"Fooling around with alternating current is just a waste of time. Nobody will use it, ever."
Thomas Edison ; 1889
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5497470 | Method and apparatus for providing a high through put cache tag controller A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory. The cache tag controller comprises memory for storing cache tags; address regis... | 03/05/1996 |
| 5481731 | Method and apparatus for invalidating a cache while in a low power state A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The pre... | 01/02/1996 |
| 5479625 | Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status registe... | 12/26/1995 |
| 5479634 | Multiprocessor cache memory unit selectively enabling bus snooping during in-circuit emulation A cache memory unit for use in a multiprocessor. The unit includes a data memory, a tag memory, a valid flag section, and an address bus, a comparator, and a clear signal producing section which produces a monitoring clear signal based on an output from t... | 12/26/1995 |
| 5448719 | Method and apparatus for maintaining and retrieving live data in a posted write cache in case of power failure A host computer including a posted write cache for a disk drive system where the posted write cache includes battery backup to protect against potential loss of data in case of a power failure, and also including means for performing a method for determin... | 09/05/1995 |
| 5440727 | Asynchronous replica management in shared nothing architectures In a partitioned database system of the Shared Nothing type, one or more secondary replicas of each partition are maintained by spooling (i.e., asynchronously sending) modified (usually called dirty) pages from the primary replica to the secondary replica... | 08/08/1995 |
| 5437017 | Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system ... | 07/25/1995 |
| 5434994 | System and method for maintaining replicated data coherency in a data processing system A system and method for maintaining data coherency in a system in which data is replicated on two or more servers. Each server is able to update the data replica present on the server. Updates are logged for each server. Reconciliation of server data repl... | 07/18/1995 |
| 5435000 | Central processing unit using dual basic processing units and combined result bus In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulat... | 07/18/1995 |
| 5432918 | Method and apparatus for ordering read and write operations using conflict bits in a write queue A method and apparatus for controlling memory access operations of a pipelined processor using a "write queue" are described. The write queue temporarily stores addresses of writes not yet made in memory. Each write queue entry includes a write-read confl... | 07/11/1995 |
| 5428757 | Method for reducing translation look aside buffer purges in a multitasking system A process for reducing translation look-aside buffer (TLB) purge overhead does so by purging the TLB only when required to avoid invalid entries. The translation look-aside buffer (TLB) contains virtual to real mappings for a particular address space. Ope... | 06/27/1995 |
| 5428630 | System and method for verifying the integrity of data written to a memory A method and system for verifying the integrity of data written to a mass memory medium. A local memory is directed by local memory control logic to store a data block that is received from a host microprocessor and that is to be written to the mass memor... | 06/27/1995 |
| 5408636 | System for flushing first and second caches upon detection of a write operation to write protected areas A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The mic... | 04/18/1995 |
| 5406504 | Multiprocessor cache examiner and coherency checker An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangemen... | 04/11/1995 |
| 5398325 | Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a ... | 03/14/1995 |
| 5379402 | Data processing device for preventing inconsistency of data stored in main memory and cache memory A comparing unit compares an address of data written into a main memory by an external device with an address of data stored in a cache memory, and a masking unit masks specific bits obtained by a result in said address comparing unit. An invalidating uni... | 01/03/1995 |
| 5379396 | Write ordering for microprocessor depending on cache hit and write buffer content An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating w... | 01/03/1995 |
| 5375220 | Multiprocessor system including a cache memory with tag copy units A multiprocessor computer system includes main memories and processors which are connected through a crossbar switching network, and a tag copying mechanism having copies of tags of caches of the processors connected to each main memory. When each of the ... | 12/20/1994 |
| 5371874 | Write-read/write-pass memory subsystem cycle Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles ... | 12/06/1994 |
| 5355477 | Method for updating a block using record-level locks by committing the update if the block has not been updated by another process otherwise spinning A Virtual Storage Access Management (VSAM) technique for maintaining data integrity of the record-level shared data in a multiprocessor system environment without the concurrency loss associated with locking at the data Control Interval (CI) or block leve... | 10/11/1994 |
| 5313631 | Dual threshold system for immediate or delayed scheduled migration of computer data files A system that places a statistical collection routine, which tracks file usage, within the path lookup process of an operating system. A statistic summarization process runs as a task of the operating system and periodically accesses the statistics collec... | 05/17/1994 |
| 5313609 | Optimum write-back strategy for directory-based cache coherence protocols A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global dir... | 05/17/1994 |
| 5301298 | Processor for multiple cache coherent protocols An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin i... | 04/05/1994 |
| 5287508 | Method and apparatus for efficient scheduling in a multiprocessor system In the present invention a predetermined number of bits are added to each entry in the process table. These bits are used to indicate the warmth of the cache with respect to the particular schedulable unit such as a process or thread of a process. The sch... | 02/15/1994 |
| 5276849 | Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of less than a word in length, the write data stored within a FIFO memory device 18 associated wit... | 01/04/1994 |
| 5269009 | Processor system with improved memory transfer means This disclosure describes an efficient method of moving data from one location in memory to another without caching the data. This includes data transfers from one main storage location to another, transfers between main and expanded storage, and transfer... | 12/07/1993 |
| 5261067 | Method and apparatus for providing synchronized data cache operation for processors in a parallel processing system Apparatus and method for insuring data cache content integrity among parallel processors is provided. Each processor has a data cache to store intermediate calculations. The data cache of each processor is synchronized with each other through the use of s... | 11/09/1993 |
| 5257367 | Data storage system with asynchronous host operating system communication link This invention provides disk drive access control apparatus for connection between a host computer and a plurality of disk drives to provide an asynchronously operating storage system. It also provides increases in performance over earlier versions thereo... | 10/26/1993 |
| 5249284 | Method and system for maintaining data coherency between main and cache memories A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data wr... | 09/28/1993 |
| 5228136 | Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity A cache coherency mechanism enabling efficient and dynamic switching between the maintenance protocols of the invalidate and update types. The mechanism can reduce traffic on the shared bus and improve the system performance. Usually each processor repeat... | 07/13/1993 |
| 5226144 | Cache controller for maintaining cache coherency in a multiprocessor system including multiple data coherency procedures A data processing system that includes a plurality of processors with at least a portion of this plurality of processors each individually connected to a cache memory for storing data for that processor. Each cache memory includes a cache controller that ... | 07/06/1993 |
| 5226146 | Duplicate tag store purge queue A method and apparatus for selectively invalidating tag data related to data stored in high speed processor cache memory systems. The tag data to be invalidated, due to processor operations and cache memory misses, is stored in two tag stores and indicia ... | 07/06/1993 |
| 5214776 | Multiprocessor system having global data replication A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write p... | 05/25/1993 |
| 5206941 | Fast store-through cache memory A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory... | 04/27/1993 |
| 5185861 | Cache affinity scheduler A computing system (50) includes N number of symmetrical computing engines having N number of cache memories joined by a system bus (12). The computing system includes a global run queue (54), an FPA global run queue, and N number of affinity run queues (... | 02/09/1993 |
| 5155831 | Data processing system with fast queue store interposed between store-through caches and a main memory A fast queue mechanism is provided which keeps a queue of changes (i.e. store actions) issued by each processor, which queue is accessible by all processors. When any processor issues a store action to a line of memory in the queue, the old data is overwr... | 10/13/1992 |
| 5136700 | Apparatus and method for reducing interference in two-level cache memories In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the ad... | 08/04/1992 |
| 4992930 | Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory A multiprocessor data processing system includes a processing unit which, together with other processing units, including input/output units, connects in common to an asynchronous bus network for sharing a main memory. At least one processing unit include... | 02/12/1991 |
| 4959777 | Write-shared cache circuit for multiprocessor system A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order ... | 09/25/1990 |
| 4933837 | Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to the invention, the memory system stores preselected instruct... | 06/12/1990 |
