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| Number | Title | Issue Date |
| 7600079 | Performing a memory write of a data unit without changing ownership of the data unit A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the secon... | 10/06/2009 |
| 7587556 | Store buffer capable of maintaining associated cache information A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively opera... | 09/08/2009 |
| 7577794 | Low latency coherency protocol for a multi-chip multiprocessor system Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the re... | 08/18/2009 |
| 7577795 | Disowning cache entries on aging out of the entry Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor... | 08/18/2009 |
| 7574567 | Monitoring processes in a non-uniform memory access (NUMA) computer system A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different nodes. The monitoring process intelligently collects data from monit... | 08/11/2009 |
| 7574566 | System and method for efficient software cache coherence Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence ... | 08/11/2009 |
| 7552288 | Selectively inclusive cache architecture In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with t... | 06/23/2009 |
| 7549024 | Multi-processing system with coherent and non-coherent modes An integrated circuit comprising a plurality of processor cores operable to perform respective data processing operations, at least one of said processor cores being configurable to operate either in a coherent multi-processing mode having access to a coherent regio... | 06/16/2009 |
| 7549025 | Efficient marking of shared cache lines One embodiment of the present invention provides a system that efficiently marks cache lines in a multi-processor computer system. The system starts by receiving a load request for a cache line from a requesting thread. Upon receiving the load request, the system lo... | 06/16/2009 |
| 7546421 | Interconnect transaction translation technique A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a multi-core processor into a fewer number of operations to be delivered to t... | 06/09/2009 |
| 7543115 | Two-hop source snoop based cache coherence protocol A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on a probe channel and a request message on a second channel from one o... | 06/02/2009 |
| 7543116 | Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator ind... | 06/02/2009 |
| 7539823 | Multiprocessing apparatus having reduced cache miss occurrences A multiprocessing apparatus includes a cache control unit which monitors a local cache access signal, outputted from a processor, for notifying an occurrence of a cache miss, and notifies pseudo information to the processor via a shared bus controller, the pseudo in... | 05/26/2009 |
| 7536513 | Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an e... | 05/19/2009 |
| 7536514 | Early return indication for read exclusive requests in shared memory architecture An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface ... | 05/19/2009 |
| 7536515 | Repeated conflict acknowledgements in a cache coherency protocol In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies. ... | 05/19/2009 |
| 7529894 | Use of FBDIMM channel as memory channel and coherence channel In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes... | 05/05/2009 |
| 7529893 | Multi-node system with split ownership and access right coherence mechanism A system may include multiple nodes, and each node may include a processing subsystem and an interface that are coupled by an address network and a data network. The nodes' interfaces may communicate over an inter-node network. Each processing subsystem may transiti... | 05/05/2009 |
| 7523265 | Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer ... | 04/21/2009 |
| 7523266 | Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution... | 04/21/2009 |
| 7519778 | System and method for cache coherence A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces... | 04/14/2009 |
| 7512741 | Two-hop source snoop based messaging protocol A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including supporting at least three protocol classes for the messaging protocol, ... | 03/31/2009 |
| 7512742 | Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a c... | 03/31/2009 |
| 7506107 | Shared memory multiprocessor system In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a subject address of ordered data reading access is compared with a su... | 03/17/2009 |
| 7502893 | System and method for reporting cache coherency state retained within a cache hierarchy of a processing node A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to receiving a memory transaction request associated with the coherency gra... | 03/10/2009 |
| 7500065 | Data processing system and method for efficient L3 cache directory management A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache li... | 03/03/2009 |
| 7500064 | Data coherence system A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device when it is initialized. If the two generations numbers are the same, t... | 03/03/2009 |
| 7496713 | Method and apparatus for maintaining cache coherency in a memory system with shared only cache memories In data processing systems that use a snoopy based cache coherence protocol and which contain a read only cache memory with a bounded range of addresses, a cache line hit is detected by assuming that, if an address contained in a request falls within the bounded ran... | 02/24/2009 |
| 7490202 | Data processing system and method for efficient L3 cache directory management A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache li... | 02/10/2009 |
| 7487298 | Disk array device, method for controlling the disk array device and storage system A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories conne... | 02/03/2009 |
| 7484043 | Multiprocessor system with dynamic cache coherency regions A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. ... | 01/27/2009 |
| 7480770 | Semi-blocking deterministic directory coherence In one embodiment, a node for a multi-node computer system comprises a coherence directory and a coherence controller. The coherence directory comprises a plurality of entries, wherein each entry corresponds to a respective coherence unit and stores a state identify... | 01/20/2009 |
| 7480771 | Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanis... | 01/20/2009 |
| 7478201 | Data processing system, cache system and method for passively scrubbing a domain indication Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one... | 01/13/2009 |
| 7478202 | Using the message fabric to maintain cache coherency of local caches of global memory Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which ... | 01/13/2009 |
| 7475195 | Data processing system, cache system and method for actively scrubbing a domain indication Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency respons... | 01/06/2009 |
| 7472228 | Read-copy update method A method for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether pre-existing references to the data elements have been removed. Plural update requests that are eligible ... | 12/30/2008 |
| 7469321 | Software process migration between coherency regions without cache purges A multiprocessor computer system has nodes which use processor state information to determine which coherent caches are required to examine a coherency transaction produced by a single originating processor's storage request. A node has dynamic coherency boundaries ... | 12/23/2008 |
| 7469322 | Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single upda... | 12/23/2008 |
| 7467262 | Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cach... | 12/16/2008 |
