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| Number | Title | Issue Date |
| 7265865 | Security for mass storage devices in imaging devices Imaging devices can have mass storage devices associated with them. In a networked environment that allows mounting of a shared resource, these mass storage devices can be viewed or even altered by anyone who can connect to the imaging device. However, unrestricted ... | 09/04/2007 |
| 7266642 | Cache residence prediction The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memor... | 09/04/2007 |
| 7266587 | System having interfaces, switch, and memory bridge for CC-NUMA operation A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment... | 09/04/2007 |
| 7266543 | System and method for accessing resources in a database A method and database management system for connecting to a database involves reusing connections for operations performed in sequence, rather than creating independent connections for each requested client connection. An application server, or layer, receives the r... | 09/04/2007 |
| 7266811 | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated progra... | 09/04/2007 |
| 7266647 | List based method and apparatus for selective and rapid cache flushes An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small sto... | 09/04/2007 |
| 7266663 | Automatic cache activation and deactivation for power reduction The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is mea... | 09/04/2007 |
| 7266643 | Information processing device The data processing unit uses, for predetermined information processing, a series of data read by uniformly accessing a predetermined address range of the external storage device through the external interface. The determination unit determines whether to write the ... | 09/04/2007 |
| 7263586 | Cache coherency for multiple independent cache of a domain Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a processing unit with multiple independent cache nits. A processing unit... | 08/28/2007 |
| 7263466 | Data management system and method A management system manages data collected at a selected frequency and data collected at a lower frequency. If the lower frequency data is abnormal, it is deleted. Deletion of the data collected at the specified frequency is dependent upon the deletion of the data c... | 08/28/2007 |
| 7263585 | Store-induced instruction coherency mechanism An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The instruction cache management logic receives an address corresponding... | 08/28/2007 |
| 7263580 | Cache flush based on checkpoint timer A data processing system is used which is provided with a computer for executing a program, and a storage unit having a cache memory for storing data transmitted as a result of execution of the program and a disk device for storing data stored in the cache memory. T... | 08/28/2007 |
| 7260628 | Event notification in storage networks A heterogeneous network includes network related hardware and software products from a plurality of vendors. The network includes a storage system configured to store data, a server configured to process requests, a switch coupling the storage system and the server ... | 08/21/2007 |
| 7260682 | Cache memory usable as scratch pad storage A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an... | 08/21/2007 |
| 7260684 | Trace cache filtering A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number ... | 08/21/2007 |
| 7257699 | Selective execution of deferred instructions in a processor that supports speculative execution One embodiment of the present invention provides a system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. During normal-execution mode, the processor issues instructi... | 08/14/2007 |
| 7257686 | Memory controller and method for scrubbing memory without using explicit atomic operations A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit ... | 08/14/2007 |
| 7257625 | Cache on demand Methods and systems are provided for delivering content from a website to a computer device. The website and computer device negotiate terms for use of a cache memory coupled to the computer device. The computer device requests content, such as web page objects, fro... | 08/14/2007 |
| 7257679 | Sharing monitored cache lines across multiple cores In one embodiment, a system comprises a first processor core and a second processor core. The first processor core is configured to communicate an address range indication identifying an address range that the first processor core is monitoring for an update. The fi... | 08/14/2007 |
| 7257715 | Semiconductor integrated circuit A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an i... | 08/14/2007 |
| 7257673 | Ternary CAM with software programmable cache policies A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers.... | 08/14/2007 |
| 7254676 | Processor cache memory as RAM for execution of boot code In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, an... | 08/07/2007 |
| 7254694 | Processors interconnect fabric with relay broadcasting and accumulation of partial responses A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plural... | 08/07/2007 |
| 7254686 | Switching between mirrored and non-mirrored volumes Provided are a method, system, and article of manufacture, wherein a request is received for switching a logical volume from one state to another state, wherein the logical volume is in a mirrored state if data corresponding to the logical volume is mirrored from a ... | 08/07/2007 |
| 7254727 | Information processor with suppressed cache coherence in low power mode An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the powe... | 08/07/2007 |
| 7254678 | Enhanced STCX design to improve subsequent load efficiency A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve op... | 08/07/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7254132 | Mobile communication system, mobile communication method, wireless base station, mobile station, and program In a wireless base station, when a newly provided control unit receives an IP packet from one mobile station (102), it refers to a destination address in control information added to the IP packet (104), and determines whether the IP packet is one to b... | 08/07/2007 |
| 7251694 | Peer-to peer name resolution protocol (PNRP) security infrastructure and method A security infrastructure and methods are presented that inhibit the ability of a malicious node from disrupting the normal operations of a peer-to-peer network. The methods of the invention allow both secure and insecure identities to be used by nodes by making the... | 07/31/2007 |
| 7251698 | Address space management in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 07/31/2007 |
| 7249224 | Methods and apparatus for providing early responses from a remote data cache According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 07/24/2007 |
| 7249245 | Globally observing load operations prior to fence instruction and post-serialization modes A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first in... | 07/24/2007 |
| 7249220 | Storage system To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnectio... | 07/24/2007 |
| 7246187 | Method and apparatus for controlling exclusive access to a shared resource in a data storage system A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the sha... | 07/17/2007 |
| 7246346 | System and method for persisting dynamically generated code in a directly addressable and executable storage medium The present invention is directed at a virtual machine environment operating on portable devices with limited resources. The virtual machine environment includes a method for compiling an intermediate language into native code wherein the native code is stored in a ... | 07/17/2007 |
| 7243136 | Approach for managing and providing content to users Content is managed and provided to users over a communications link using a differencing engine. The differencing engine is configured to selectively cause content to be refreshed in a cache. Specifically, the differencing engine is configured to detect whether a mo... | 07/10/2007 |
| 7243229 | Exclusive access control apparatus and method A computing system and an exclusive access control method are provided for preventing degraded performance of a network caused by exclusive access control, and for permitting a computer to exclusively access a storage area irrespective of whether a storage has an ex... | 07/10/2007 |
| 7243208 | Data processor and IP module for data processor In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixed... | 07/10/2007 |
| 7240174 | System and method for migrating data between memories An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device. The new memory location being where data, which is being migrated from... | 07/03/2007 |
| 7240170 | High/low priority memory Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write informati... | 07/03/2007 |
