Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8117399 | Processing of coherent and incoherent accesses at a uniform cache Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit ... | 02/14/2012 |
| 8112590 | Methods and apparatus for reducing command processing latency while maintaining coherence In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory ... | 02/07/2012 |
| 8108619 | Cache management for partial cache line operations A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache... | 01/31/2012 |
| 8108620 | Cooperative caching technique A method of caching data in a global cache distributed amongst a plurality of computing devices, comprising providing a global cache for caching data accessible to interconnected client devices, where each client contributes a portion of its main memory to the globa... | 01/31/2012 |
| 8108621 | Data cache with modified bit array A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the c... | 01/31/2012 |
| 8108618 | Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus control... | 01/31/2012 |
| 8103834 | Coherence protocol with dynamic privatization Embodiments of the present invention provide a system that maintains coherence between cache lines in a computer system by using dynamic privatization. During operation, the system starts by receiving a request for a read-only copy of a cache line from a processor. ... | 01/24/2012 |
| 8103835 | Low-cost cache coherency for accelerators Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing... | 01/24/2012 |
| 8099558 | Fairness mechanism for starvation prevention in directory-based cache coherence protocols Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linke... | 01/17/2012 |
| 8095739 | Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarc... | 01/10/2012 |
| 8090913 | Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a... | 01/03/2012 |
| 8069313 | Method and system for managing cache invalidation In one embodiment the present invention includes a method and system for managing cache invalidation. In one embodiment, connection information to a database in stored in an intermediate cache management module. If changes are made to objects in the database, the ob... | 11/29/2011 |
| 8069312 | Apparatus, circuit and method of controlling memory initialization An apparatus includes a first memory which includes a plurality of memory regions, a second memory which stores initializing information indicating whether each of the memory regions is initialized, the second memory controlling a coherency between the first memory ... | 11/29/2011 |
| 8055851 | Line swapping scheme to reduce back invalidations in a snoop filter In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresp... | 11/08/2011 |
| 8051250 | Systems and methods for pushing data A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push ... | 11/01/2011 |
| 8046539 | Method and apparatus for the synchronization of distributed caches A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching i... | 10/25/2011 |
| 8041898 | Method, system and apparatus for reducing memory traffic in a distributed memory system The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. Th... | 10/18/2011 |
| 8037252 | Method for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determi... | 10/11/2011 |
| 8032716 | System, method and computer program product for providing a new quiesce state A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received a... | 10/04/2011 |
| 8019947 | Technique for thread communication and synchronization A technique for thread synchronization and communication. More particularly, embodiments of the invention pertain to managing communication and synchronization among two or more threads of instructions being executing by one or more microprocessors or microprocessor... | 09/13/2011 |
| 8015362 | Method and system for handling cache coherency for self-modifying code A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amo... | 09/06/2011 |
| 8010750 | Network on chip that maintains cache coherency with invalidate commands A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configure... | 08/30/2011 |
| 8010749 | Multi-node computer system with proxy transaction to read data from a non-owning memory device A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network and a data network. In response to rece... | 08/30/2011 |
| 7991964 | Pre-coherence channel A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment,... | 08/02/2011 |
| 7987321 | Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which e... | 07/26/2011 |
| 7984244 | Method and apparatus for supporting scalable coherence on many-core products through restricted exposure In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the fir... | 07/19/2011 |
| 7984245 | Storage system, storage subsystem and storage control method Proposed is a storage system capable of preventing the compression of a cache memory caused by data remaining in a cache memory of a storage subsystem without being transferred to a storage area of an external storage, and maintaining favorable I/O processing perfor... | 07/19/2011 |
| 7971002 | Maintaining instruction coherency in a translation-based computer system architecture Methods and systems for maintaining instruction coherency in a translation-based computer system architecture are described. A translation coherence cache memory can be used to store a memory page reference that identifies a memory page. The cache memory also stores... | 06/28/2011 |
| 7971003 | Cache coherency in a shared-memory multiprocessor system A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache ... | 06/28/2011 |
| 7958318 | Coherency maintaining device and coherency maintaining method A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of dat... | 06/07/2011 |
| 7953936 | Hiding conflict, coherence completion and transaction ID elements of a coherence protocol According to one embodiment of the invention, an apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache... | 05/31/2011 |
| 7953935 | Cache memory system, and control method therefor A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a... | 05/31/2011 |
| 7949833 | Transparent level 2 cache controller A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed b... | 05/24/2011 |
| 7949831 | Maintaining cache coherence using load-mark metadata to deny invalidation of load-marked cache lines Embodiments of the present invention provide a system that maintains load-marks on cache lines. The system includes: (1) a cache which accommodates a set of cache lines, wherein each cache line includes metadata for load-marking the cache line, and (2) a local cache... | 05/24/2011 |
| 7949832 | Latency reduction for cache coherent bus-based cache In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on ... | 05/24/2011 |
| 7945738 | Multi-node computer system employing a reporting mechanism for multi-node transactions A system may include a node and an additional node coupled by an inter-node network. The node includes an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active de... | 05/17/2011 |
| 7945739 | Structure for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design struct... | 05/17/2011 |
| 7934060 | Lightweight coherency control protocol for clustered storage system A lightweight coherency control protocol ensures consistency of data containers, such as a file, and associated data buffers stored on one or more volumes served by a plurality of nodes, e.g., storage systems, connected as a cluster. Each data buffer is associated w... | 04/26/2011 |
| 7934061 | Methods and arrangements to manage on-chip memory to reduce memory latency Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow... | 04/26/2011 |
| 7934059 | Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plura... | 04/26/2011 |
