Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8190826 | Write combining cache with pipelined synchronization Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions wit... | 05/29/2012 |
| 8127082 | Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally ta... | 02/28/2012 |
| 8103833 | Cache memory and a method for servicing access requests A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a s... | 01/24/2012 |
| 8028130 | Pipeline structure for a shared memory protocol A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a su... | 09/27/2011 |
| 7502892 | Decoupling request for ownership tag reads from data read operations Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not r... | 03/10/2009 |
| 7401189 | Pipelining D states for MRU steerage during MRU/LRU member allocation A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A l... | 07/15/2008 |
| 7398358 | Method and apparatus for high performance branching in pipelined microsystems A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and mult... | 07/08/2008 |
| 7376793 | Cache coherence protocol with speculative writestream A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operati... | 05/20/2008 |
| 7370150 | System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached... | 05/06/2008 |
| 7369447 | Random cache read A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein t... | 05/06/2008 |
| 7366851 | Processor, method, and data processing system employing a variable store gather window A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple sto... | 04/29/2008 |
| 7363468 | Load address dependency mechanism system and method in a high frequency, low power processor system The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory ... | 04/22/2008 |
| 7360022 | Synchronizing an instruction cache and a data cache on demand In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instr... | 04/15/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7353310 | Hierarchical memory access via pipelining with deferred arbitration A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage... | 04/01/2008 |
| 7350037 | Digital signal processor and digital signal processing method enabling concurrent program download and execution A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program coun... | 03/25/2008 |
| 7340568 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 03/04/2008 |
| 7334089 | Methods and apparatus for providing cache state information According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 02/19/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7325101 | Techniques for reducing off-chip cache memory accesses Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cac... | 01/29/2008 |
| 7302527 | Systems and methods for executing load instructions that avoid order violations Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to sear... | 11/27/2007 |
| 7290089 | Executing cache instructions in an increased latency mode For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle a... | 10/30/2007 |
| 7284096 | Systems and methods for data caching Systems and methods are provided for data caching. An exemplary method for data caching may include establishing a FIFO queue and a LRU queue in a cache memory. The method may further include establishing an auxiliary FIFO queue for addresses of cache lines that hav... | 10/16/2007 |
| 7281091 | Storage controlling apparatus and data storing method A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. Th... | 10/09/2007 |
| 7281110 | Random access memory controller with out of order execution A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge... | 10/09/2007 |
| 7277991 | Method, system, and program for prefetching data into cache Provided are a method, system and program for prefetching data into cache. A prefetch command is processed that indicates at least one conditional statement and at least one block to prefetch from storage to cache in response to determining that the conditional stat... | 10/02/2007 |
| 7278136 | Reducing processor energy consumption using compile-time information A method, for use in a processor, includes mapping a first data access having less than a predetermined memory footprint to a first memory area, and mapping a second data access having greater than the predetermined memory footprint to a second memory area. The meth... | 10/02/2007 |
| 7275112 | Efficient serialization of bursty out-of-order results A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating tha... | 09/25/2007 |
| 7269179 | Control mechanisms for enqueue and dequeue operations in a pipelined network processor Common control for enqueue and dequeue operations in a pipelined network processor includes receiving in a queue manager a first enqueue or dequeue with respect to a queue and receiving a second enqueue or dequeue request in the queue manager with respect to the que... | 09/11/2007 |
| 7263585 | Store-induced instruction coherency mechanism An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The instruction cache management logic receives an address corresponding... | 08/28/2007 |
| 7260684 | Trace cache filtering A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number ... | 08/21/2007 |
| 7260686 | System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. T... | 08/21/2007 |
| 7249224 | Methods and apparatus for providing early responses from a remote data cache According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 07/24/2007 |
| 7243203 | Pipeline circuit for low latency memory The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer compris... | 07/10/2007 |
| 7243192 | Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM us... | 07/10/2007 |
| 7234027 | Instructions for test & set with selectively enabled cache invalidate A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the... | 06/19/2007 |
| 7228362 | Out-of-order servicing of read requests with minimal additional storage Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be... | 06/05/2007 |
| 7225300 | Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to... | 05/29/2007 |
| 7209393 | Semiconductor memory device and method for multiplexing write data thereof A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device further includes a memory core region including an array of memory cells... | 04/24/2007 |
| 7206230 | Use of data latches in cache operations of non-volatile memories Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a w... | 04/17/2007 |
