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| Number | Title | Issue Date |
| 5410668 | Reconfigurable cache memory which can selectively inhibit access to damaged segments in the cache memory A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for accessing the plurality of segments in parallel for access by the CPU, and a second access path ... | 04/25/1995 |
| 5297270 | Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size A system includes a main memory having a plurality of sections which each include a plurality of selectively addressable storage locations, a cache memory, and an accessing arrangement for successively requesting data from respective locations in the main... | 03/22/1994 |
| 5157774 | System for fast selection of non-cacheable address ranges using programmed array logic A fast logic system for decoding addresses for the purpose of designating areas of memory as noncacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-... | 10/20/1992 |
| 5136691 | Methods and apparatus for caching interlock variables in an integrated cache memory Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selective... | 08/04/1992 |
