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| Number | Title | Issue Date |
| 8108617 | Method to bypass cache levels in a cache coherent system Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit ... | 01/31/2012 |
| 7849269 | System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In ... | 12/07/2010 |
| 7849270 | System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In ... | 12/07/2010 |
| 7836261 | Managing caching of data on a client Embodiments include retrieving data of a web page from a remote system in response to a request for the web page. It is determined that the web page is indicated in a data structure that indicates web pages not to be cached in a cache of a web browser on a data proc... | 11/16/2010 |
| 7356650 | Cache apparatus and method for accesses lacking locality Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a ... | 04/08/2008 |
| 7277399 | Hardware-based route cache using prefix length The present invention defines a system and method of routing packets using a hardware-based route cache with prefix length. When a router receives a packet, the router first searches for the routing information in the hardware-based route cache and if a match is fou... | 10/02/2007 |
| 7254673 | Provision of a victim cache within a storage cache hierarchy Apparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode wherein data read for storage in the first cache is also stored in the second cache, and is capable of operat... | 08/07/2007 |
| 7254727 | Information processor with suppressed cache coherence in low power mode An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the powe... | 08/07/2007 |
| 7251694 | Peer-to peer name resolution protocol (PNRP) security infrastructure and method A security infrastructure and methods are presented that inhibit the ability of a malicious node from disrupting the normal operations of a peer-to-peer network. The methods of the invention allow both secure and insecure identities to be used by nodes by making the... | 07/31/2007 |
| 7237065 | Configurable cache system depending on instruction type A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control l... | 06/26/2007 |
| 7225436 | Java hardware accelerator using microcode engine A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™... | 05/29/2007 |
| 7206916 | Partial address compares stored in translation lookaside buffer A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation ... | 04/17/2007 |
| 7185149 | Selective storage in a cache memory device A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predeterm... | 02/27/2007 |
| 7174415 | Specialized memory device A specialized memory chip which includes an embedded application specific signal processing unit ASSPU. The ASSPU handles one or more predetermined tasks instead of a main processing unit. The ASSPU and the main processing unit can access memory on the memory chip s... | 02/06/2007 |
| 7167964 | Memory defragmentation in chipcards The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the location of source and target of the copy operations which are to be perform... | 01/23/2007 |
| 7136984 | Low power cache architecture In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstr... | 11/14/2006 |
| 7117315 | Method and apparatus for creating a load module and a computer product thereof Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area... | 10/03/2006 |
| 7103608 | Method and mechanism for storing and accessing data A method and mechanism is disclosed for implementing storage and retrieval of data in a computing system. Data compression is performed on stored data by reducing or eliminating duplicate values in a database block. Duplicated values are eliminated within the set of... | 09/05/2006 |
| 7098822 | Method for handling data A method, device and computer program for handling a data stream comprising a number of data objects, wherein for at least one of these data objects a decision is made whether a compression is conducted based on a value representing a compression factor of the data ... | 08/29/2006 |
| 7089397 | Method and system for caching attribute data for matching attributes with physical addresses A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical addr... | 08/08/2006 |
| 7089394 | Optimally mapping a memory device In one embodiment of the present invention, a method includes observing disk requests for a drive associated with a memory device; and mapping the memory device based on observing the disk requests. ... | 08/08/2006 |
| 7080169 | Receiving data from interleaved multiple concurrent transactions in a FIFO memory having programmable buffer zones A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing betwe... | 07/18/2006 |
| 7076612 | Cache interface circuit for automatic control of cache bypass modes and associated power savings A cache interface circuit includes a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to the processor in response to processor requests. A main memory interface provides for issuing main memory access ... | 07/11/2006 |
| 7062631 | Method and system for enforcing consistent per-physical page cacheability attributes A method and system for enforcing consistent per-physical page cacheability attributes is disclosed. The method for enforcing consistent per-physical page cacheability attributes maintains memory coherency within a processor addressing memory, such as by comparing a... | 06/13/2006 |
| 7058773 | System and method for managing data in a distributed system A memory system includes a client device and multiple memory devices. The client device communicates an operation request pertaining to a particular data object to one memory device. Referencing a host table, the memory device identifies multiple memory devices asso... | 06/06/2006 |
| 7058783 | Method and mechanism for on-line data compression and in-place updates A method and mechanism is disclosed for implementing storage and compression in a computer system. Each granular portion of a file can be individually stored in either a compressed storage unit or an uncompressed storage unit. The storage units can be allocated apri... | 06/06/2006 |
| 7055006 | System and method for blocking cache use during debugging A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to... | 05/30/2006 |
| 7051152 | Method and system of improving disk access time by compression A data storage system using compression to increase performance. The system has a hardware compression/decompression engine for performing data compression on a data block and performing data decompression of the data block. A controller is coupled to the hardware c... | 05/23/2006 |
| 7039901 | Software shared memory bus The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in... | 05/02/2006 |
| 7017009 | Cache memory device A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predeterm... | 03/21/2006 |
| 6981112 | Dynamic cache disable An apparatus, program product and method utilize a cache payback parameter for selectively and dynamically disabling caching for potentially cacheable operations performed in connection with a memory. The cache payback parameter is tracked concurrently with the perf... | 12/27/2005 |
| 6938143 | Dynamically adaptive buffer mechanism A system supports allocating buffer storage for multiple buffers from a common storage area and dynamically reconfiguring the common storage area to shift buffer storage between buffers. A buffer mechanism controls access to buffer storage allocated within the commo... | 08/30/2005 |
| 6934812 | Media player with instant play capability A media player and a method for operating a media player are disclosed. A media program is able to substantially immediately begin playing after a media play selection has been made. Through intelligent operation, the media program is able to start playing even befo... | 08/23/2005 |
| 6918071 | Yield improvement through probe-based cache size reduction A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache oper... | 07/12/2005 |
| 6907477 | Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality o... | 06/14/2005 |
| 6865650 | System and method for hierarchical data storage A system and method for storing data, the system having one or more storage devices, caches data from a sender into a first random-access structure located in a first cache level, caches data from the first cache level into a log structure located in a second cache ... | 03/08/2005 |
| 6681297 | Software controlled cache configuration based on average miss rate A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a res... | 01/20/2004 |
| 6587928 | Scheme for segregating cacheable and non-cacheable by port designation Requests are identified as being for a cacheable object or a non-cacheable object according to information included in a Uniform Resource Locator (URL) associated with the object. For example, the URL may include a port designation for requests for cachea... | 07/01/2003 |
| 6574708 | Source controlled cache allocation A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cac... | 06/03/2003 |
| 6415362 | Method and system for write-through stores of varying sizes A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, whe... | 07/02/2002 |
