Bizarre Patents
A kissing shield comprised of a thin, flexible membrane and a frame or holder.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8060702 | Information reproducing apparatus and information reproducing method According to one embodiment, an information reproducing apparatus includes a memory, a decoder, an intermediate memory which is disposed between the memory and the decoder and which temporarily stores, in succession, the data that are supplied from the memory and th... | 11/15/2011 |
| 8055850 | Prioritization of directory scans in cache A method, system, and computer program product for prioritizing directory scans in cache by a processor is provided. While traversing a directory in the cache, one of attempting to acquire a lock for a directory entry and attempting to acquire access to a track in t... | 11/08/2011 |
| 8032715 | Data processor The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable... | 10/04/2011 |
| 8015361 | Memory-centric page table walker The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests... | 09/06/2011 |
| 7937534 | Performing direct cache access transactions based on a memory access data structure Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to det... | 05/03/2011 |
| 7904662 | System and program product for validating remotely cached dynamic content web pages Under the present invention, when a request for a web page is received from a client on a server, the web page is built and analyzed for cacheability. If the web page is cacheable, an entity tag is generated. The entity tag generally identifies the various sources o... | 03/08/2011 |
| 7865669 | System and method for dynamically selecting the fetch path of data for improving processor performance A system and method for dynamically selecting the data fetch path for improving the performance of the system improves data access latency by dynamically adjusting data fetch paths based on application data fetch characteristics. The application data fetch character... | 01/04/2011 |
| 7788451 | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a writ... | 08/31/2010 |
| 7769955 | Multiple thread instruction fetch from different cache levels A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarch... | 08/03/2010 |
| 7730264 | Adaptively reducing memory latency in a system In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportuni... | 06/01/2010 |
| 7725659 | Alignment of cache fetch return data relative to a thread A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sect... | 05/25/2010 |
| 7698507 | Protecting system management mode (SMM) spaces against cache attacks A computing system may comprise a processor and a memory controller hub coupled by an external bus such as the front side bus. The processor may also comprise a cache. The processor may operate in SMM and the memory coupled to the memory controller hub may comprise ... | 04/13/2010 |
| 7631149 | Systems and methods for providing fixed-latency data access in a memory system having multi-level caches Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memo... | 12/08/2009 |
| 7594081 | Direct access to low-latency memory A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface... | 09/22/2009 |
| 7587555 | Program thread synchronization The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more processors is provided. An address for data for each of a plurality of pr... | 09/08/2009 |
| 7430641 | System method and circuit for retrieving into cache data from one or more mass data storage devices According to some embodiments of the present invention, a data storage system may include a plurality of controllers connected or otherwise associated with one or more mass data storage devices. One controller may signal to one or more other controllers an indicatio... | 09/30/2008 |
| 7421726 | Method of seamlessly replacing disc-based video streams with memory-based video streams in a video-on-demand system In a video-on-demand system, disc-based video streams are seamlessly replaced with memory-based video streams. This is achieved by first switching each disc-based video stream to a mixed video stream; and later, switching each mixed video stream to a memory-based vi... | 09/02/2008 |
| 7401188 | Method, device, and system to avoid flushing the contents of a cache by not inserting data from large requests A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write request if the length of the data requested is less than the threshold ... | 07/15/2008 |
| 7401187 | Method and apparatus for reading a data store In an electronic computing system, an instruction is provided as to whether to cache in a region of a memory of the system an attribute of a context if and when the context is accessed in a permanent storage device. When the context is accessed in the permanent stor... | 07/15/2008 |
| 7395381 | Method and an apparatus to reduce network utilization in a multiprocessor system A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion ... | 07/01/2008 |
| 7392350 | Method to operate cache-inhibited memory mapped commands to access registers In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Set... | 06/24/2008 |
| 7380067 | IO-stream adaptive write caching policy adjustment A method for performing adaptive write caching in a storage virtualization subsystem is disclosed. In this method, criteria associated with an operation state of the storage virtualizalion subsystem for performing write caching are first defined. Then, the character... | 05/27/2008 |
| 7376807 | Data processing system having address translation bypass and method therefor In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and conver... | 05/20/2008 |
| 7373460 | Media drive and command execution method thereof Embodiments of the present invention provide a media drive capable of improving command processing performance by, when a plurality of commands is queued, shortening seek time and rotational latency, and also effectively making use of the shortened period of time. I... | 05/13/2008 |
| 7373453 | Method and apparatus of interleaving memory bank in multi-layer bus system A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals gene... | 05/13/2008 |
| 7366049 | Apparatus and method for updating data in a dual port memory A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an add... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7360020 | Method for improving cache-miss performance A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system mem... | 04/15/2008 |
| 7360021 | System and method for completing updates to entire cache lines with address-only bus operations A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits o... | 04/15/2008 |
| 7360015 | Preventing storage of streaming accesses in a cache In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the str... | 04/15/2008 |
| 7356650 | Cache apparatus and method for accesses lacking locality Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a ... | 04/08/2008 |
| 7356649 | Semiconductor data processor A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for o... | 04/08/2008 |
| 7353338 | Credit mechanism for multiple banks of shared cache Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared ca... | 04/01/2008 |
| 7353445 | Cache error handling in a multithreaded/multi-core processor In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the c... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7353345 | External observation and control of data in a computing processor A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a d... | 04/01/2008 |
| 7353513 | Method and apparatus for establishing a bound on the effect of task interference in a cache memory A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is the maximum number of “live” frames of a given task that are coex... | 04/01/2008 |
| 7349942 | Storage medium having a manageable file directory structure A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and system can be used to limit the number of items within the directory, d... | 03/25/2008 |
| 7350026 | Memory based cross compare for cross checked systems A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, req... | 03/25/2008 |
| 7346735 | Virtualized load buffers A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information w... | 03/18/2008 |
