Quotables
"Telephone, n. An invention of the devil which abrogates some of the advantages of making a disagreeable person keep his distance. "
Ambose Bierce
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6360298 | Load/store instruction control circuit of microprocessor and load/store instruction control method A load/store instruction control method of a microprocessor according to the present invention has a feature as follows. The circuit implements non-blocking cache which does not allow a pipeline process of a microprocessor to stop even if a cache miss by ... | 03/19/2002 |
| 6351796 | Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values stored in the lower level cache, the relevancy information i... | 02/26/2002 |
| 6349358 | Magnetic disc control apparatus capable of detecting a near sequential I/O and storing it to a cache memory, and a system thereof A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor, which has an I/O history storage table for storing a transfe... | 02/19/2002 |
| 6345338 | Adapting resource use to improve performance in a caching memory system A memory system, and a method for controlling prestaging activities based upon the availability of resources within the memory system. Prestage requests are stored in a shared memory accessible to a resource controller and one or more memory controllers. ... | 02/05/2002 |
| 6343359 | Result forwarding cache An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics--complexity, power, and timing--that are not significantly impacted by the number of stages in the microproce... | 01/29/2002 |
| 6341334 | Bridge method, bus bridge, and multiprocessor system In a bridge method, bus bridge, and multiprocessor system for predicting request signals to be received, issuance of and data-caching in response to request signals is based on prediction results, and responses are sent to request signals that are actuall... | 01/22/2002 |
| 6341335 | Information processing system for read ahead buffer memory equipped with register and memory controller An information processing system which reduces an access latency from a memory read request of a processor to a response thereto and also prevents reduction of the effective performance of a system bus caused by an increase in the access latency. In the i... | 01/22/2002 |
| 6339811 | Rotationally optimized seek initiation Methods and control systems for delaying a seek once a command is received to further load a buffer with read look ahead data are described. The methods involve calculating when or at what point the prefetching should cease and a seek should be initiated ... | 01/15/2002 |
| 6338133 | Measured, allocation of speculative branch instructions to processor execution units A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue whi... | 01/08/2002 |
| 6338115 | Advanced read cache management A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, as well as co... | 01/08/2002 |
| 6324623 | Computing system for implementing a shared cache In a multi-threaded computing environment, a shared cache system reduces the amount of redundant information stored in memory. A cache memory area provides both global readable data and private writable data to processing threads. A particular processing ... | 11/27/2001 |
| 6321312 | System and method for controlling peripheral device memory access in a data processing system A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and te... | 11/20/2001 |
| 6321301 | Cache memory device with prefetch function and method for asynchronously renewing tag addresses and data during cache miss states A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch co... | 11/20/2001 |
| 6321296 | SDRAM L3 cache using speculative loads with command aborts to lower latency A computer system having a cache for providing data to the system's processing unit(s), wherein the cache controller selectively aborts speculative accesses to its data array. The cache initiates a transfer of data by speculatively transmitting an associa... | 11/20/2001 |
| 6317811 | Method and system for reissuing load requests in a multi-stream prefetch design A method and system for reissuing load requests in a multi-stream prefetch engine of a data processing system is provided. A read transaction is received from a transaction requester, and the read transaction has a base address and a prefetch stream ident... | 11/13/2001 |
| 6317810 | Microprocessor having a prefetch cache A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipel... | 11/13/2001 |
| 6314494 | Dynamically size configurable data buffer for data cache and prefetch cache memory A size configurable data buffer includes a plurality of data cache memory registers and a variable number of prefetch memory registers. A computer controller determines the allocation of the data buffer which is data cache memory registers or prefetch mem... | 11/06/2001 |
| 6314472 | Abort of DRAM read ahead when PCI read multiple has ended A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled... | 11/06/2001 |
| 6314493 | Branch history cache Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual h... | 11/06/2001 |
| 6310743 | Seek acoustics reduction with minimized performance degradation A method of controlling an actuator in a disc drive to perform a seek operation prior to a read operation is disclosed. A radial distance between the initial track and the target track is determined. A rotational distance between the initial head rotation... | 10/30/2001 |
| 6311260 | Method for perfetching structured data A method for prefetching structured data, and more particularly a mechanism for observing address references made by a processor, and learning from those references the patterns of accesses made to structured data. Structured data means aggregates of rela... | 10/30/2001 |
| 6304962 | Method and apparatus for prefetching superblocks in a computer processing system A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current s... | 10/16/2001 |
| 6298424 | Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch pri... | 10/02/2001 |
| 6295583 | Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering A processor of a multiprocessor system is configured to transmit a full probe to a cache associated with the processor to transfer data from the stored data of the cache. The data corresponding to the full probe is transferred during a time period. A firs... | 09/25/2001 |
| 6282626 | No stall read access-method for hiding latency in processor memory accesses The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If m... | 08/28/2001 |
| 6282614 | Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches An apparatus and method for reducing the power consumption of a multi-cache microprocessor dynamically predicts the misses of an ith -level (Li) cache. This method predicts the misses in Li and accesses the i+1 level cache... | 08/28/2001 |
| 6279081 | System and method for performing memory fetches for an ATM card The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM... | 08/21/2001 |
| 6279076 | Reproducing apparatus and caching method The invention provides a method and apparatus for caching data in a highly efficient fashion during a data reproducing process thereby reducing the access time. In the case where it is determined that the type of a data request is not a sequential data re... | 08/21/2001 |
| 6275918 | Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based... | 08/14/2001 |
| 6275899 | Method and circuit for implementing digital delay lines using delay caches A circuit for implementing digital delay lines that includes a main memory, a cache memory, and a processor. The main memory implements at least one digital delay line, as many delay lines as required by a digital signal processing (DSP) program running o... | 08/14/2001 |
| 6272590 | Method and system for prefetching sequential data in a data storage system A method and system in a data storage system for reading stored data from the data storage system, where the data storage system comprises N data storage drives and an associated cache, where data and calculated parity are striped across the N data storag... | 08/07/2001 |
| 6266742 | Algorithm for cache replacement In a computer system in which caching is utilized for improving performance, a method for determining whether an uncached object should be cached, and, if so, which objects, if any, should be removed from a cache to make room for the new uncached object. ... | 07/24/2001 |
| 6263404 | Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system A memory cache sequencer circuit manages the operation of a memory cache and cache buffer so as to efficiently forward memory contents being delivered to the memory cache via the cache buffer, to a multithreading processor awaiting return of those memory ... | 07/17/2001 |
| 6260116 | System and method for prefetching data A method and system for prefetching data from storage and storing the data in a cache memory for use by an executing program includes means for detecting when a program has entered a processing loop and has completed at least one pass through the processi... | 07/10/2001 |
| 6260115 | Sequential detection and prestaging methods for a disk storage subsystem A method for detecting and remembering multiple sequential access patterns made from a host to a memory system having one or more logical storage devices. Once a sequential access pattern is detected, one or more tracks are requested to be prestaged ahead... | 07/10/2001 |
| 6260113 | Method and apparatus defining a miss list and producing dial-in hit ratios in a disk storage benchmark A method and apparatus for defining a random miss list and producing a desired hit ratio in a benchmark test of computer disk storage are disclosed. The disk area to be tested is divided into N tracks. A random miss list of L tracks is defined as specifie... | 07/10/2001 |
| 6253289 | Maximizing sequential read streams while minimizing the impact on cache and other applications In a data storage system a number of records are prefetched from large volume storage devices for transfer to a cache in order to return requested records to a host computer in response to a read request from the host computer. If a previous prefetch is n... | 06/26/2001 |
| 6253288 | Hybrid cache/SIRO buffer system A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arri... | 06/26/2001 |
| 6247107 | Chipset configured to perform data-directed prefetching A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated by the processors to the main memory, and returns the dat... | 06/12/2001 |
| 6243807 | Optimizing cache data load required for functions in loop routine by sequentially collecting data in external memory for single block fetch The performance of a computer architecture having cache memory is optimized by reorganizing the structure of information before such information is written into an external memory coupled to a processor. Specifically, loops of repeated processing steps ar... | 06/05/2001 |
