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| Number | Title | Issue Date |
| 8190825 | Arithmetic processing apparatus and method of controlling the same A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from t... | 05/29/2012 |
| 8185696 | Virtual memory window with dynamic prefetching support Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPG... | 05/22/2012 |
| 8166251 | Data prefetcher that adjusts prefetch stream length based on confidence In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data cache, and the prefetch unit is configured to issue prefetches predicted by... | 04/24/2012 |
| 8166250 | Information processing unit, program, and instruction sequence generation method An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address r... | 04/24/2012 |
| 8166252 | Processor and prefetch support program A processor loads a program from a main memory, detects a register updating instruction, and registers the address of the register updating instruction in a register-producer table storing unit. Moreover, the processor loads the program to detect a memory access ins... | 04/24/2012 |
| 8161245 | Method and apparatus for performing data prefetch in a multiprocessor system A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is ini... | 04/17/2012 |
| 8161246 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configure... | 04/17/2012 |
| 8156286 | Processor and method for using an instruction hint to prevent hardware prefetch from using certain memory accesses in prefetch calculations A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon pr... | 04/10/2012 |
| 8156287 | Adaptive data prefetch A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power ... | 04/10/2012 |
| 8145846 | Memory system having nonvolatile and buffer memories, and reading method thereof Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of reque... | 03/27/2012 |
| 8140769 | Data prefetcher In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load operations that miss the data cache, and includes a memory configured to s... | 03/20/2012 |
| 8140768 | Jump starting prefetch streams across page boundaries A method, processor, and data processing system for enabling utilization of a single prefetch stream to access data across a memory page boundary. A prefetch engine includes an active streams table in which information for one or more scheduled prefetch streams are ... | 03/20/2012 |
| 8135915 | Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator A method, apparatus, and computer instructions for providing hardware assistance to prefetch data during execution of code by a process or in the data processing system. In response to loading an instruction in the code into a cache, a determination is made by a pro... | 03/13/2012 |
| 8131938 | Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, ... | 03/06/2012 |
| 8127080 | Wake-and-go mechanism with system address bus transaction master A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data v... | 02/28/2012 |
| 8127081 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 02/28/2012 |
| 8122196 | System and procedure for rapid decompression and/or decryption of securely stored data A procedure and system reduces latency in restoring encrypted or compressed and encrypted data through a security appliance. The security appliance is coupled to a sequential access device and is configured to encrypt or compress and encrypt data provided by an init... | 02/21/2012 |
| 8117398 | Prefetch termination at powered down memory bank boundary in shared memory controller A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. ... | 02/14/2012 |
| 8108615 | Prefetching controller using a counter A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a controller connected to the register for changing the counter value w... | 01/31/2012 |
| 8108616 | Processing a data stream by accessing one or more hardware registers Disclosed are a method, a system, and a program product for processing a data stream by accessing one or more hardware registers of a processor. In one or more embodiments, a first program instruction or subroutine can associate a hardware register of the processor ... | 01/31/2012 |
| 8103832 | Method and apparatus of prefetching streams of varying prefetch depth Method and apparatus of prefetching streams of varying prefetch depth dynamically changes the depth of prefetching so that the number of multiple streams as well as the hit rate of a single stream are optimized. The method and apparatus in one aspect monitor a plura... | 01/24/2012 |
| 8086804 | Method and system for optimizing processor performance by regulating issue of pre-fetches to hot cache sets A method for pre-fetching data. The method includes obtaining a pre-fetch request. The pre-fetch request identifies new data to pre-fetch from memory and store in a cache. The method further includes identifying a set in the cache to store the new data and identifyi... | 12/27/2011 |
| 8082398 | Data prefetching using indirect addressing There is a need for providing a data processor capable of easily prefetching data from a wide range. A central processing unit is capable of performing a specified instruction that adds an offset to a value of a register to generate an effective address for data. Th... | 12/20/2011 |
| 8078806 | Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l... | 12/13/2011 |
| 8078805 | Method and system for communicating with a universal serial bus device A caching filter driver which is adapted for communicating with a universal serial bus (USB) mass storage device, the caching filter driver is adapted to: (a) receive a first reading request for a first size data from a USB mass storage driver; (b) determine if requ... | 12/13/2011 |
| 8074029 | Processor equipped with a pre-fetch function and pre-fetch control method A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and ... | 12/06/2011 |
| 8069311 | Methods for prefetching data in a memory storage structure A method includes detecting a cache miss. The method further includes, in response to detecting the cache miss, traversing a plurality of linked memory nodes in a memory storage structure being used to store data to determine if the memory storage structure is a bin... | 11/29/2011 |
| 8069310 | Methods and systems for incorporating sequential stream read requests into prefetch management for data storage having a cache memory Data units are prefetched into a cache memory by executing a first prefetch task to prefetch a first prefetch series of data units from off-cache. A first prefetch operation is executed to prefetch and store a first selected set of data units. Decisions are made abo... | 11/29/2011 |
| 8060701 | Apparatus and methods for low-complexity instruction prefetch system When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction c... | 11/15/2011 |
| 8051249 | Method for preloading data to improve data-retrieval times The present invention discloses methods for improving data-retrieval times from a non-volatile storage device. A method for preloading data to improve data-retrieval times from a non-volatile storage device, the method including the steps of: providing a cache memor... | 11/01/2011 |
| 8032711 | Prefetching from dynamic random access memory to a static random access memory Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with ... | 10/04/2011 |
| 8032712 | Storage system for staging data in random access area There is provided a storage system accessed by a host computer, comprising: an interface coupled to the host computer; a processor coupled the interface; a memory coupled to the processor; and a storage device for storing the data. The storage device comprises a fir... | 10/04/2011 |
| 8032714 | Methods and systems for caching data using behavioral event correlations A method is disclosed including a client accessing a cache for a value of an object based on an object identification (ID), initiating a request to a cache loader if the cache does not include a value for the object, the cache loader performing a lookup in an object... | 10/04/2011 |
| 8032713 | Structure for handling data access A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative... | 10/04/2011 |
| 8015360 | Memory system having nonvolatile and buffer memories, and reading method thereof Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of reque... | 09/06/2011 |
| 8010748 | Cache structure for peer-to-peer distribution of digital objects A method for the distribution of digital objects in a peer-to-peer network is disclosed. The digital objects are distributed in a plurality of pieces. At least some of a plurality of peers are connected to other ones of the plurality of peers and at least one of the... | 08/30/2011 |
| 8006040 | Data storage device and method thereof A microprocessor 18 in a control device 13 of a data storage device determines that the read request has a sequential access property, when a transfer size of data specified by a read request from a host computer 11 is the same as a preset pre-f... | 08/23/2011 |
| 8006041 | Prefetch processing apparatus, prefetch processing method, storage medium storing prefetch processing program A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains c... | 08/23/2011 |
| 8001332 | Adaptive caching for high volume extract transform load process A method, system, and medium related to a mechanism to cache key-value pairs of a lookup process during an extract transform load process of a manufacturing execution system. The method includes preloading a cache with a subset of a set of key-value pairs stored in ... | 08/16/2011 |
| 7996624 | Prefetch unit In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the proces... | 08/09/2011 |
