Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 5043885 | Data cache using dynamic frequency based replacement and boundary criteria A cache directory keeps track of which blocks are in the cache, the number of times each block in the cache has been referenced after aging at least a predetermined amount (reference count), and the age of each block since the last reference to that block... | 08/27/1991 |
| 5025366 | Organization of an integrated cache unit for flexible usage in cache system design Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance w... | 06/18/1991 |
| 4996641 | Diagnostic mode for a cache A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing ... | 02/26/1991 |
| 4980823 | Sequential prefetching with deconfirmation A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bi... | 12/25/1990 |
| 4959771 | Write buffer for a digital processing system The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a "smart" buffer. The write buffer has multiple buffer locations for storing data receive... | 09/25/1990 |
| 4928239 | Cache memory with variable fetch and replacement schemes An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data b... | 05/22/1990 |
| 4920478 | Cache system used in a magnetic disk controller adopting an LRU system A magnetic disk controller incorporating a cache memory which employs an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entries have LRU counter fields, a host system issuing a read/writ... | 04/24/1990 |
| 4905139 | Cache memory system with improved re-writing address determination scheme involving history of use A cache memory system having an improved area addressing scheme for rewriting is disclosed. The cache memory system comprises a cache memory having a plurality of memory areas, a first detection circuit for designating the least recently accessed area by ... | 02/27/1990 |
| 4905141 | Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification A CPU has N-1 ports for concurrently making memory requests and transferring data using a cache with M partitions. Each partition includes a cache directory partition and a corresponding cache data store partition. Each port has a Partition Look-Aside Tab... | 02/27/1990 |
| 4835686 | Cache system adopting an LRU system, and magnetic disk controller incorporating it A cache system employing an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entires have LRU counter fields, a host system issuing a read/write command to which an arbitrary LRU setting v... | 05/30/1989 |
| 4814746 | Data compression method Communications between a Host Computing System and a number of remote terminals is enhanced by a data compression method which modifies the data compression method of Lempel and Ziv by addition of new character and new string extensions to improve the com... | 03/21/1989 |
| 4811203 | Hierarchial memory system with separate criteria for replacement and writeback without replacement In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to s... | 03/07/1989 |
| 4785395 | Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units. For completely independent operation, each processing unit is allocated one-half of th... | 11/15/1988 |
| 4783735 | Least recently used replacement level generating apparatus A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value... | 11/08/1988 |
| 4736287 | Set association memory system A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultane... | 04/05/1988 |
| 4648069 | Character generator A character generator uses a first memory having a permanent resident area and an overlay area. A second memory stores patterns of all characters. The permanent resident area stores character patterns having the highest frequency of use. The overlay area ... | 03/03/1987 |
| 4636946 | Method and apparatus for grouping asynchronous recording operations The disclosure relates to demotion of data to a backing store (disk storage apparatus--DASD) from a random access cache in a peripheral data storage system. A cache replacement control list, such as a least recently used (LRU) list is scanned in a soon-to... | 01/13/1987 |
| 4607331 | Method and apparatus for implementing an algorithm associated with stored information A circuit and method for implementing a predetermined data replacement algorithm associated with a fast, low capacity cache, such as least recently used (LRU), which is fast and which minimizes circuitry is provided. A latch stores the present status of t... | 08/19/1986 |
| 4571674 | Peripheral storage system having multiple data transfer rates Fast and slow channels are attached to a cached peripheral storage system, having a front store and a backing store preferably with a plurality of data storage devices. The peripheral data storage device data transfer rate is not greater than the data rat... | 02/18/1986 |
| 4530055 | Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor pa... | 07/16/1985 |
| 4509119 | Method for managing a buffer pool referenced by batch and interactive processes Method for managing a buffer pool shared by sequential and random processes. A data base manager includes a buffer manager which: (1) maintains a normal least recently used (LRU) buffer chain and a sequential LRU buffer chain, the sequential LRU buffer ch... | 04/02/1985 |
| 4490782 | I/O Storage controller cache system with prefetch determined by requested record's position within data block In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future... | 12/25/1984 |
| 4467411 | Scheduling device operations in a buffered peripheral subsystem Data transfers between respective buffer segments and data source-sinks, such as peripheral data storage devices, are scheduled as a series of transfers based upon most recent, next most recent, to the least recent usage of the buffer segments by a utiliz... | 08/21/1984 |
| 4463420 | Multiprocessor cache replacement under task control The disclosure describes a novel cache directory entry replacement method and means for central processors (CPs) in a multiprocessor (MP) based on task identifiers (TIDs) provided in each directory entry to identify the program task which inserted the res... | 07/31/1984 |
| 4463424 | Method for dynamically allocating LRU/MRU managed memory among concurrent sequential processes Short traces of consecutive CPU references to storage are accumulated and processed to ascertain hit ratio as a function of cache size. From this determination, an allocation of cache can be made. Because this determination requires minimal processing tim... | 07/31/1984 |
| 4458310 | Cache memory using a lowest priority replacement circuit A data processing system having a processor, main memory, and a cache memory system which implements the least recently used replacement algorithm in replacing cache memory words with main memory words. The cache memory system is comprised of a cache cont... | 07/03/1984 |
| 4437155 | Cache/disk subsystem with dual aging of cache entries When a processor issues a read or write command to read one or more words from a disk, a cache store is checked to see if a copy of the segment(s) containing the word(s) are present therein. If a copy of the segment is not present in the cache store then ... | 03/13/1984 |
| 4349875 | Buffer storage control apparatus A buffer storage control apparatus selectively employs the conventional "least-recently-used" (LRU) algorithm or the "all-used" (AU) algorithm to determine which block of data in the buffer storage unit is to be replaced by new data. The AU algorithm reli... | 09/14/1982 |
| 4322795 | Cache memory utilizing selective clearing and least recently used updating An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement... | 03/30/1982 |
| 4186438 | Interactive enquiry system Described is an interactive enquiry system in which a complete data base is contained at a host computer. Local terminal sub-systems are remotely connected to the host with each local sub-system containing a local data base. Each local data base is dynami... | 01/29/1980 |
| 4059850 | Memory system word group priority device with least-recently used criterion A word group priority device for use in a data processing system having a first store and a relatively faster but smaller capacity second store, which device assigns priorities to word groups on a least recently used basis. Upon the read-out or read-in of... | 11/22/1977 |
| 4008460 | Circuit for implementing a modified LRU replacement algorithm for a cache A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for th... | 02/15/1977 |
| 3967247 | Storage interface unit A storage interface unit adapted to serve as a high speed buffer between plural requestor units and a relatively low speed main memory in a data processing system. The high speed buffer provides temporary storage for a limited number of blocks of data sto... | 06/29/1976 |
