Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8099557 | Push for sharing instruction In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a ... | 01/17/2012 |
| 8082397 | Private slot Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of... | 12/20/2011 |
| 8078804 | Method and arrangement for cache memory management, related processor architecture A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in... | 12/13/2011 |
| 8028129 | Dynamically re-classifying data in a shared cache In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of... | 09/27/2011 |
| 8006039 | Method, system, and computer program product for merging data A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input... | 08/23/2011 |
| 8001330 | L2 cache controller with slice directory and unified cache structure A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache di... | 08/16/2011 |
| 7991960 | Adaptive comparison control in a data store Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at l... | 08/02/2011 |
| 7970999 | Cache memory for a scalable information distribution system An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive sig... | 06/28/2011 |
| 7890701 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching includes providing a cache community of peer members and a master member. A master member volunteers to leave the cache community upon which decision a peer member is selected to become the new master member. ... | 02/15/2011 |
| 7853753 | Distributive network control Included are systems and methods for distributive network control. Also embodiment of a method includes receiving an indication related to recording data stored on a local cache and determining whether to remotely store at least a portion of the data. Some embodimen... | 12/14/2010 |
| 7831773 | Utilizing cache information to manage memory access and cache utilization A method and system of managing data access in a shared memory cache of a processor are disclosed. The method includes probing one or more memory addresses that map to a subset of the shared memory cache and sensing a plurality of events in the one or more memory ad... | 11/09/2010 |
| 7827357 | Providing an inclusive shared cache among multiple core-cache clusters In one embodiment, the present invention includes a method for receiving requested data from a system interconnect interface in a first scalability agent of a multi-core processor including a plurality of core-cache clusters, storing the requested data in a line of ... | 11/02/2010 |
| 7818503 | Method and apparatus for memory utilization One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also i... | 10/19/2010 |
| 7809891 | Wait-free parallel data cache A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier stor... | 10/05/2010 |
| 7730262 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client ma... | 06/01/2010 |
| 7730261 | Multicore memory management system A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directl... | 06/01/2010 |
| 7725657 | Dynamic quality of service (QoS) for a shared cache In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator wit... | 05/25/2010 |
| 7711900 | Method, system and program product for equitable sharing of a CAM table in a network switch in an on-demand environment A method, system and program product for equitable sharing of a CAM (Content Addressable Memory) table among multiple users of a switch. The method includes reserving buffers in the table to be shared, the remaining buffers being allocated to each user. The method f... | 05/04/2010 |
| 7698504 | Cache line marking with shared timestamps Embodiments of the present invention provide a system that marks cache lines using shared timestamps. During operation, the system starts a transaction for a thread, wherein starting the transaction involves recording the value of an active timestamp and incrementin... | 04/13/2010 |
| 7694076 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client ma... | 04/06/2010 |
| 7689773 | Methods and apparatus for estimating fair cache miss rates on a chip multiprocessor A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates ... | 03/30/2010 |
| 7627718 | Frozen ring cache A processor having multiple cores and a multiple cache segments, each core associated with one of the cache segments, the cache segments interconnected by a data communication ring, and logic to disallow operation of the ring at a startup event and to execute an ini... | 12/01/2009 |
| 7603522 | Blocking aggressive neighbors in a cache subsystem A system and method for managing a cache subsystem. A system comprises a plurality of processing entities, a cache shared by the plurality of processing entities, and circuitry configured to manage allocations of data into the cache. Cache controller circuitry is co... | 10/13/2009 |
| 7584327 | Method and system for proximity caching in a multiple-core system Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable effi... | 09/01/2009 |
| 7577792 | Heterogeneous processors sharing a common cache A multi-core processor providing heterogeneous processor cores and a shared cache is presented. ... | 08/18/2009 |
| 7571285 | Data classification in shared cache of multiple-core processor In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of... | 08/04/2009 |
| 7552284 | Least frequently used eviction implementation Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction ... | 06/23/2009 |
| 7549022 | Avoiding cache line sharing in virtual machines Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system and oversees memory access by the guest. Because cache lines are asso... | 06/16/2009 |
| 7536511 | CPU mode-based cache allocation for image data An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive ... | 05/19/2009 |
| 7529890 | System, apparatus and method for facilitating on-chip testing A system, apparatus and method enabling common memory pool tests to be conducted in a multiprocessing system by using substantially the same system components that are used during a normal mode of operation. Under normal mode of operation, a data cache interface fac... | 05/05/2009 |
| 7526611 | Unified processor cache model in multiprocessor system Exemplary embodiments include a multiprocessor system including: a plurality of processors in operable communication with an address manager and an memory controller; and a unified cache in operable communication with the address manager, wherein the unified cache i... | 04/28/2009 |
| 7523263 | Storage plug-in based on shared closures Methods for a treatment of cached objects are described. In one embodiment, a first shared closure for a first application is cached into a shared memory with a first virtual machine that is executed on a CPU. A second shared closure for a second application is cach... | 04/21/2009 |
| 7516277 | Cache monitoring using shared memory A system and method to monitor caches of at least one Java virtual machine (“JVM”). A program is operated on the at least one JVM. Objects associated with the program are cached within a local cache of the JVM. Cache status information about the local cache is g... | 04/07/2009 |
| 7502888 | Symmetric multiprocessor system Systems, methods, and device are provided for symmetric multiprocessor (SMP) systems. One method embodiment includes creating a child process for each processor in the SMP. An event address register (EAR) associated with each processor is used to record information ... | 03/10/2009 |
| 7500059 | Inter-processor communication method using a shared cache memory in a storage system When communications among a plurality of processors employed in a network storage system are required, any of the processors initiating a communication on the transmission side issues a request to an I/O processing apparatus, which is used for controlling a disk uni... | 03/03/2009 |
| 7475193 | Separate data and coherency cache directories in a shared cache in a multiprocessor system A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two se... | 01/06/2009 |
| 7469319 | Methods and apparatuses for mappable shared cache management Methods and apparatuses enable separate management of shared data structures and shared data objects referenced by the shared data structures. The shared data structures are stored in a first memory, and the shared data structures are separately managed from the ref... | 12/23/2008 |
| 7434001 | Method of accessing cache memory for parallel processing processors A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction proces... | 10/07/2008 |
| 7434002 | Utilizing cache information to manage memory access and cache utilization In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed p... | 10/07/2008 |
| 7434006 | Non-speculative distributed conflict resolution for a cache coherency protocol A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward... | 10/07/2008 |
