Quotables
"It is my heart-warmed and world-embracing Christmas hope and aspiration that all of us, the high, the low, the rich, the poor, the admired, the despised, the loved, the hated, the civilized, the savage (every man and brother of us all throughout the whole earth), may eventually be gathered together in a heaven of everlasting rest and peace and bliss, except the inventor of the telephone. "
Mark Twain ; Christmas greetings, 1890
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| Number | Title | Issue Date |
| 8443148 | System-wide quiescence and per-thread transaction fence in a distributed caching agent Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction ... | 05/14/2013 |
| 8423717 | Multi-core processing cache image management A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to... | 04/16/2013 |
| 8417891 | Shared cache memories for multi-core processors Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller i... | 04/09/2013 |
| 8407420 | System, apparatus and method utilizing early access to shared cache pipeline for latency reduction A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machi... | 03/26/2013 |
| 8402222 | Caching for heterogeneous processors A multi-core processor providing heterogeneous processor cores and a shared cache is presented. ... | 03/19/2013 |
| 8392659 | Extending cache capacity on multiple-core processor systems A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cacheli... | 03/05/2013 |
| 8359434 | Distributive network control Included are systems and methods for distributive network control. In addition, embodiment of a method includes receiving an indication related to recording data stored on a local cache and determining whether to remotely store at least a portion of the data. Some e... | 01/22/2013 |
| 8347038 | Optimizing memory copy routine selection for message passing in a multicore architecture In one embodiment, the present invention includes a method to obtain topology information regarding a system including at least one multicore processor, provide the topology information to a plurality of parallel processes, generate a topological map based on the to... | 01/01/2013 |
| 8307160 | Interface apparatus, calculation processing apparatus, interface generation apparatus, and circuit generation apparatus There is provided is an interface apparatus including: a stream converter receiving write-addresses and write-data, storing the received data in a buffer, and sorting the stored write-data in the order of the write-addresses to output the write-data as stream-data; ... | 11/06/2012 |
| 8296522 | Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage ... | 10/23/2012 |
| 8275944 | Distributive network control Included are systems and methods for distributive network control. In addition, embodiment of a method includes receiving an indication related to recording data stored on a local cache and determining whether to remotely store at least a portion of the data. Some e... | 09/25/2012 |
| 8271734 | Method and system for converting data formats using a shared cache coupled between clients and an external memory A system and method for converting data from one format to another in a processing pipeline architecture. Data is stored in a shared cache that is coupled between one or more clients and an external memory. The shared cache provides storage that is used by multiple ... | 09/18/2012 |
| 8271735 | Cache-coherency protocol with held state A new “held” (“H”) cache-coherency state is introduced for directory-based multiprocessor systems. Using the held state enables embodiments of the present invention to track sharers that have a shared copy of a cache line after a directory runs out of space ... | 09/18/2012 |
| 8261021 | Cache control device and control method In order to control an access request to the cache shared between a plurality of threads, a storage unit for storing a flag provided in association with each of the threads is included. If the threads enter the execution of an atomic instruction, a defined value is ... | 09/04/2012 |
| 8205044 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select... | 06/19/2012 |
| 8156285 | Heterogeneous processors sharing a common cache A multi-core processor providing heterogeneous processor cores and a shared cache is presented. ... | 04/10/2012 |
| 8151057 | Shared cache for point-to-point connected processing nodes A shared cache is point-to-point connected to a plurality of point-to-point connected processing nodes, wherein the processing nodes may be integrated circuits or multiprocessing systems. In response to a local cache miss, a requesting processing node issues a broad... | 04/03/2012 |
| 8140765 | Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req... | 03/20/2012 |
| 8122195 | Instruction for pre-fetching data and releasing cache lines A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store an... | 02/21/2012 |
| 8099557 | Push for sharing instruction In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a ... | 01/17/2012 |
| 8082397 | Private slot Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of... | 12/20/2011 |
| 8078804 | Method and arrangement for cache memory management, related processor architecture A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in... | 12/13/2011 |
| 8028129 | Dynamically re-classifying data in a shared cache In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of... | 09/27/2011 |
| 8006039 | Method, system, and computer program product for merging data A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input... | 08/23/2011 |
| 8001330 | L2 cache controller with slice directory and unified cache structure A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache di... | 08/16/2011 |
| 7991960 | Adaptive comparison control in a data store Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at l... | 08/02/2011 |
| 7970999 | Cache memory for a scalable information distribution system An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive sig... | 06/28/2011 |
| 7890701 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching includes providing a cache community of peer members and a master member. A master member volunteers to leave the cache community upon which decision a peer member is selected to become the new master member. ... | 02/15/2011 |
| 7853753 | Distributive network control Included are systems and methods for distributive network control. Also embodiment of a method includes receiving an indication related to recording data stored on a local cache and determining whether to remotely store at least a portion of the data. Some embodimen... | 12/14/2010 |
| 7831773 | Utilizing cache information to manage memory access and cache utilization A method and system of managing data access in a shared memory cache of a processor are disclosed. The method includes probing one or more memory addresses that map to a subset of the shared memory cache and sensing a plurality of events in the one or more memory ad... | 11/09/2010 |
| 7827357 | Providing an inclusive shared cache among multiple core-cache clusters In one embodiment, the present invention includes a method for receiving requested data from a system interconnect interface in a first scalability agent of a multi-core processor including a plurality of core-cache clusters, storing the requested data in a line of ... | 11/02/2010 |
| 7818503 | Method and apparatus for memory utilization One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also i... | 10/19/2010 |
| 7809891 | Wait-free parallel data cache A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier stor... | 10/05/2010 |
| 7730261 | Multicore memory management system A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directl... | 06/01/2010 |
| 7730262 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client ma... | 06/01/2010 |
| 7725657 | Dynamic quality of service (QoS) for a shared cache In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator wit... | 05/25/2010 |
| 7711900 | Method, system and program product for equitable sharing of a CAM table in a network switch in an on-demand environment A method, system and program product for equitable sharing of a CAM (Content Addressable Memory) table among multiple users of a switch. The method includes reserving buffers in the table to be shared, the remaining buffers being allocated to each user. The method f... | 05/04/2010 |
| 7698504 | Cache line marking with shared timestamps Embodiments of the present invention provide a system that marks cache lines using shared timestamps. During operation, the system starts a transaction for a thread, wherein starting the transaction involves recording the value of an active timestamp and incrementin... | 04/13/2010 |
| 7694076 | Method and system for dynamic distributed data caching A method and system for dynamic distributed data caching is presented. The method includes providing a cache community comprising at least one peer. Each peer has an associated first content portion indicating content to be cached by the respective peer. A client ma... | 04/06/2010 |
| 7689773 | Methods and apparatus for estimating fair cache miss rates on a chip multiprocessor A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates ... | 03/30/2010 |
