Class 711/127 - Interleaved

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter wherein consecutive cache memory locations
No. of patents: 147
Last issue date: 01/10/2012

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Number	Title	Issue Date
8095735	Memory interleave for heterogeneous computing A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block acc...	01/10/2012
7475192	Cache organization for power optimized memory access An N-set associative cache organization is disclosed. The cache organization comprises a plurality of SRAMs, wherein the data within the SRAMs such that a first 1/N of a plurality of cache lines is within a first portion of the plurality of SRAMs and last 1/N portio...	01/06/2009
7433429	De-interleaver method and system In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer. ...	10/07/2008
7386691	Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output dat...	06/10/2008
7365632	Resistive elements using carbon nanotubes Resistive elements include a patterned region of nanofabric having a predetermined area, where the nanofabric has a selected sheet resistance; and first and second electrical contacts contacting the patterned region of nanofabric and in spaced relation to each other...	04/29/2008
7360023	Method and system for reducing power consumption in a cache memory A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of bloc...	04/15/2008
7350016	High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memor...	03/25/2008
7340568	Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit....	03/04/2008
7321949	Memory device including self-ID information Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each ba...	01/22/2008
7320053	Banking render cache for multiple access A cache memory system may be is organized as a set of numbered banks. If two clients need to access the cache, a contention situation may be resolved by a contention resolution process. The contention resolution process may be based on relative priorities of the cli...	01/15/2008
7318114	System and method for dynamic memory interleaving and de-interleaving In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each decoder of a given memory controller may be independently configurable to m...	01/08/2008
7313768	Register file and method for designing a register file A register file includes a plurality of registers for storing therein data, a plurality of input ports for receiving therethrough the data to be stored in the registers, and a plurality of output ports for delivering therethrough the data stored in the registers. Ea...	12/25/2007
7296112	High bandwidth memory management using multi-bank DRAM devices The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are sto...	11/13/2007
7287145	System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are...	10/23/2007
7275112	Efficient serialization of bursty out-of-order results A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating tha...	09/25/2007
7269179	Control mechanisms for enqueue and dequeue operations in a pipelined network processor Common control for enqueue and dequeue operations in a pipelined network processor includes receiving in a queue manager a first enqueue or dequeue with respect to a queue and receiving a second enqueue or dequeue request in the queue manager with respect to the que...	09/11/2007
7266651	Method for in-place memory interleaving and de-interleaving A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address ...	09/04/2007
7240160	Multiple-core processor with flexible cache directory scheme A multiple-core processor providing a flexible cache directory scheme. In one embodiment, a processor may include a second-level cache including a number of cache banks and a respective number of cache directories corresponding to the cache banks. The processor may ...	07/03/2007
7228393	Memory interleaving A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been dev...	06/05/2007
7219185	Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction fiel...	05/15/2007
7174426	Interleave pre-checking in front of shared caches with pipelined access The invention relates to a method and respective system for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments, wherein the cache memory is accessed by a plurality of competing cache memory requests via a num...	02/06/2007
7171439	Use of hashed content addressable memory (CAM) to accelerate content-aware searches A server is provided having a port for receiving a data request that includes an identifier (e.g., an HTTP request that includes a URL). Recognition logic is provided to extract the identifier, using delimiters present in the data request. Padding logic fixes the le...	01/30/2007
7149824	Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ...	12/12/2006
7146480	Configurable memory system A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality of transport cells that can be configured to implement various trans...	12/05/2006
7139784	Dead timestamp identification and elimination The performance of an application is improved by identifying and eliminating items with dead time-stamps and eliminating work on items with irrelevant time-stamps. An algorithm executing in each node of a task graph computes and propagates guarantees which are used ...	11/21/2006
7130211	Interleave control device using nonvolatile ferroelectric memory An interleave control device using a nonvolatile ferroelectric memory is disclosed. More specifically, a memory interleave structure using a nonvolatile ferroelectric register configured to individually control interleaves of banks is disclosed. In an embodiment of ...	10/31/2006
7127586	Prefetching hints A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination.	10/24/2006
7127547	Processor with multiple linked list storage feature A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list data structures are stored in memory circuitry associated with the pr...	10/24/2006
7117310	Systems and methods for cache synchronization between redundant storage controllers Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in ...	10/03/2006
7117315	Method and apparatus for creating a load module and a computer product thereof Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area...	10/03/2006
7114040	Default locality selection for memory objects based on determining the type of a particular memory object One embodiment disclosed relates to a method of selecting a default locality for a memory object requested by a process running on a CPU in a multiprocessor system. A determination is made as to whether the memory object comprises a shared-memory object. If the memo...	09/26/2006
7089379	Large high bandwidth memory system A memory system is divided into memory subsystems. Each subsystem includes a slave controller. Each slave controller is coupled to a serial link. A master controller is coupled to the slave controllers via the serial links, and the master controller is capable of in...	08/08/2006
7085887	Processor and processor method of operation In one embodiment, the present invention is directed to a processor that comprises an instruction pipeline for executing processor instructions wherein the processor instructions define a memory access size and a cache memory for storing cache lines in a plurality o...	08/01/2006
7076601	Memory controller and data processing system A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high...	07/11/2006
7076614	System and method for optimizing bus bandwidth utilization by grouping cache write-backs A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at lea...	07/11/2006
7073029	Storage system using fast storage and log-structured storage A computer storage system includes a controller and a storage device array. The storage device array includes a first sub-array and a fast storage device sub-array. The first sub-array includes one or more log-structured storage devices storing data. The fast storag...	07/04/2006
7068281	Pixel pages optimized for GLV Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source, providing pixel data for pixels in a first order, each pixel in a frame havi...	06/27/2006
7065531	Combining computer programs A file is created that includes two computer programs. The first computer program is combined with a second computer program in the file, for example, by adding the first computer program to the file and appending the second computer program to the file. A file loca...	06/20/2006
7051171	Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and pr...	05/23/2006
7039762	Parallel cache interleave accesses with address-sliced directories A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split...	05/02/2006

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Class 711/127 - Interleaved